Reductant-Assisted Self-Assembly with Cu/Sn Microbump for Three-Dimensional Heterogeneous Integration

Abstract

To establish liquid-assisted assembly processes applicable to heterogeneous system integrations, we present flip-chip self-assembly of dies with Cu/Sn microbumps using the difference in droplet wetting between hydrophilic and hydrophobic areas. Flip-chip self-assembly is assisted by a water-soluble flux that has high surface tension comparable to that of pure water and contains an additive of a reducing agent for metal oxides. Control of the additive concentration in the flux provides high wettability contrast that enable spontaneous and precise alignment of chips to hydrophilic areas formed on substrates within 5 µm in alignment accuracy. In the subsequent chip bonding process, the reductant can eliminate the metal oxide layer and improve the solder wettability of Sn to the corresponding electrode pads formed on the chips. In addition, we confirm, through electrical characteristic evaluation after thermal compression bonding, that the resulting daisy chain formed between the substrates and self-assembled chips with the flux shows sufficiently low contact resistance of below 20 mΩ/bump without disconnection.

(Invited) Self-Assembly Based Multichip-to-Wafer Bonding Technologies for 3D/Hetero Integration

“…The flux diluted in water can remove the oxidized thin surface while self-assembled. We have demonstrated Cu/Sn microbump bonding with low contact resistances (8), (9). The second one is the use of NCF (non-conductive film) that is typically laminated on bumped wafers prior to saw dicing.…”

Vertical-cavity surface-emitting laser chip bonding by surface-tension-driven self-assembly for optoelectronic heterogeneous integration

“…Optical path for intra-chip, chip-to-chip, and on-board, VCSEL, PD, optical TSV, lens parts, and optical path conversion components transmission in high-performance computing systems, highend servers, and data center networks. [34][35][36] However, compared with other optical devices such as photodiodes and optical modulators, light-emitting device arrays such as LDs and VCSELs cannot be monolithically integrated owing to their low process compatibility with Si devices. 37) Therefore, the emitting device arrays require high-precision massively parallel assembly procedures.…”

“…So far, most of the self-assembly works have dealt with highly symmetric square, polygonal, circular, or low-aspect-ratio rectangular chips. 10,[18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34] Broesch et al have reported the effects of chip geometries on restoring force and torque by extending the symmetric squares to rectangles with high aspect ratios using simulation software. 38) However, only a few papers on liquid-mediated self-assembly even with symmetric square chips have described their alignment accuracies in detail.…”

“…We have applied for the first time surface tension-driven chip self-assembly to 3D LSI fabrication 26) and developed advanced self-assembly technologies including alignment, bonding, and packaging based on multichip-to-wafer stacking for 3D heterogeneous system integration composed of various devices, materials, and dimensions. 10,[27][28][29][30][31][32][33][34] Rectangular multichannel light-emitting devices in a rectangular shape with high length-to-width aspect ratio are promising candidates for ultraparallel and ultrahigh-speed optical data…”

Direct multichip-to-wafer 3D integration technology using flip-chip self-assembly of NCF-covered known good dies

“…We have previously reported precise flip-chip selfassembly and microbump interconnections using KGDs with fine-pitch In/Au bumps [12][13][14] and with Cu/Sn bumps [15,16], respectively. This paper proposes a new flip-chip selfassembly method using KGDs covered with NCFs to realize high-throughput and highly-reliable microbump interconnections for advanced direct multichip-to-wafer 3D integration.…”