Direct multichip-to-wafer 3D integration technology using flip-chip self-assembly of NCF-covered known good dies

Abstract

We demonstrated surface tension-driven self-assembly and microbump bonding using NCF (non-conductive film)-covered chips with Cu/Sn-Ag microbumps for highthroughput and high-yield direct multichip-to-wafer 3D integration. The NCF is a promising candidate to completely fill gaps between fine-pitch microbumps, and is essential for realizing highly-reliable microbump-to-microbump interconnections. Here, by applying the self-assembly method with strong water surface tension, the NCF-covered chips were precisely aligned to hydrophilic assembly sites defined on host Si substrates in a face-down manner with alignment accuracies of approximately 1 µm. The self-assembled chips having Cu/Sn-Ag microbumps covered with NCF were thermally compressed to obtain electrical joints between the chips and substrate after the self-assembly process. The resulting daisy chains showed good electrical characteristics with contact resistance of 53 mΩ/joint.

Non-conductive film underfill for 3D integration of 20 pm-thick LSI wafers with fine Cu-TSVs

“…The μ-bump size and pitch values are in the range from 5 -10 μm and 15 -40 μm, respectively. More details regarding the self-assembly of NCF covered die/wafer to the interposer is found elsewhere [4][5].…”

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration

“…However, the NCP technology involves sequential low-throughput dispensing processes, whereas the NCF technology called wafer-level underfilling still requires pick-and-place assembly after dicing of NCF-laminated wafers. We have presented a fully wafer-level underfill technology using a new NCF technology combined with MCtW capillary self-assembly [ 15 , 16 ]. The NCF technology can reduce the pitches of solder/Cu microbump down to 30 µm or less.…”