Reduction of Power and Delay in Shift Register using MTCMOS Technique

Gour, Sonam; Soni, Gaurav Kumar

doi:10.1109/icoei48184.2020.9143026

Cited by 4 publications

(2 citation statements)

References 4 publications

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“…Sleep transistors, typically high-threshold PMOS or NMOS, are employed to cut power to specific sections of a device. MTCMOS devices are known for their reduced power consumption during idle states and lower latency [22,23]. The circuit was developed with possible changes in the size and quantity of HVT and LVT transistors along with a super cut-off mechanism.…”

Section: Methodsmentioning

confidence: 99%

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Sudhakar,

Stan

2023

Electronics

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The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.

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Section: Methodsmentioning

confidence: 99%

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Sudhakar,

Stan

2023

Electronics

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“…S. Gour et al; (2020) [4] Reduction of Power and Delay in Shift Register using MTCMOS Technique Analysis of the energy delayed in HSPICE is done using the Cosmos Scope software. Use the BPTM model files for 32 and 45nm to construct the Shift Register.…”

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confidence: 99%

Simulation of Low-Power Shift Registers Using the MTCMOS Method with a Wide Selection of Transistors

Manokaran¹,

Zainuddin²

2022

Malaysian J. Sci. Adv. Tech.

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The method of huge integrating involves implementing a significant transistor count in an extremely condensed space. Combinatorial logic has shown to be particularly effective in quantum computing as well as other designing applications. In VLSI design, the primary goal is to cut down on power consumption as well as latency. For the purpose of establishing technology and supporting the increased use of electrical machines, it is vital to decrease sub-threshold current flowing for large strains. This research explores the feasibility of implementing a shift register and without the Multi-threshold CMOS (MTCMOS) approach. At the process technology of 0.18 µm, 0.12 µm, and 90 nm, an investigation into the power loss and transmission delay characteristics of a variety of flip-flops is carried out. As technology gets shrunk, the amount of power lost through leakage rises. Using the greatest technique among all run time strategies, namely MTCMOS, helps to limit the amount of power lost due to leakage. The purpose of this article is to give a comparison between various traditional flip-flops and the TSPC flip-flop with regard to power usage, diffusion delays, product of delay-power (PDP), area, and power flow using the findings obtained from the Microwind simulator.

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Tunable Low Voltage Low Power Operational Transconductance Amplifier For Biomedical Application

Shankar¹,

Soni

Singh³

et al. 2021

2021 Fourth International Conference on Electrical, Computer and Communication Technologies (ICECCT)

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Reduction of Power and Delay in Shift Register using MTCMOS Technique

Cited by 4 publications

References 4 publications

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Simulation of Low-Power Shift Registers Using the MTCMOS Method with a Wide Selection of Transistors

Tunable Low Voltage Low Power Operational Transconductance Amplifier For Biomedical Application

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