Simulation of Low-Power Shift Registers Using the MTCMOS Method with a Wide Selection of Transistors

Abstract

The method of huge integrating involves implementing a significant transistor count in an extremely condensed space. Combinatorial logic has shown to be particularly effective in quantum computing as well as other designing applications. In VLSI design, the primary goal is to cut down on power consumption as well as latency. For the purpose of establishing technology and supporting the increased use of electrical machines, it is vital to decrease sub-threshold current flowing for large strains. This research explores the feasibility of implementing a shift register and without the Multi-threshold CMOS (MTCMOS) approach. At the process technology of 0.18 µm, 0.12 µm, and 90 nm, an investigation into the power loss and transmission delay characteristics of a variety of flip-flops is carried out. As technology gets shrunk, the amount of power lost through leakage rises. Using the greatest technique among all run time strategies, namely MTCMOS, helps to limit the amount of power lost due to leakage. The purpose of this article is to give a comparison between various traditional flip-flops and the TSPC flip-flop with regard to power usage, diffusion delays, product of delay-power (PDP), area, and power flow using the findings obtained from the Microwind simulator.

Design and Analysis of Full Adder Using 0.6 Micron CMOS Technology

“…However, as more multiplexers is used, the delay of the full adder will increase as well due to the port-switching and extra I/O (Input/Output) signals that increases as more multiplexers is added. Previous works have been covered in [12] and [13] respectively.…”