The design of a full adder involves the use of logic gates so that the design can convert 8 inputs to create a byte-wide adder and to force the carry bit to the other adder.   However, the uses of multiplexers to replace the logic gates in the construction of the full adder is proven to be possible due to the function of the multiplexers to act as the digital switch in the system that provides the flow of digital information from multiple inputs into an output. This research aims to explore the possibility of implementing the multiplexers into the design of the full adder and to analyse the different possible full adder design using the multiplexers. Using the multiplexers also allows for fewer logic gates to be used in the design of the full adder, which reduces the overall area coverage of the full adder. However, adding multiplexers does not make a complete adder more efficient and may slow it down. Thus, this article compares a conventional full adder with logic gates, a full adder with two 2:1 multiplexers, and a full adder with six 2:1 multiplexers in terms of power usage, time delay of the Sum and Carry outputs, and technology (0.6 μm).

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As modern wireless communication systems move towards 5G implementation, the system must provide sophisticated and ubiquitous service and flexibility. Therefore, Filtered Orthogonal Frequency Division Multiple Access (F-OFDMA) is one of the most suitable modulation techniques used in 5G systems to achieve efficient and reliable wireless communication.  Other than that, F-OFDMA also has good quality rather than OFDM since it provides a better result of high side lobes and enlarges the scale of the spectrum analyzer. However, one of the significant problems in the F-OFDMA system is the high peak-to-average power ratio (PAPR), affecting the system's overall performance and causing high transmit power at the transmitter. In this paper, combination of Arithmetic Coding (AC) and Huffman coding (HC) with Asymmetric Numeral Systems (ANS) provide better performance for PAPR as well as bit error rate (BER) in F-OFDMA. Both AC and HC are proposed to combine with ANS and Quasi-Cyclic Low-Density Parity Check (QC-LDPC) since it provides a good result to defeat the high PAPR. BER and PAPR performance were compared for the AC and HC with ANS QC-LDPC. Based on the results, ANS-AC-QCLDPC proved as the best joint method has 35.25% improvement for PAPR while BER has 89.87%. This research also justified that ANS with Arithmetic-QCLDPC and Huffman-QCLDPC give better BER results as well.