Reduction of STI/active stress on 0.18 μm SOI devices through modification of STI process

En, W.G.; Ju, Dong-Hyuk; Chan, Darin; Chan, Syin; Karlsson, Olov

doi:10.1109/soic.2001.957997

Cited by 3 publications

(3 citation statements)

References 2 publications

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“…6,7) Thus, such isolation is not useful for conventional power and highfrequency devices, and the most efficient way to decrease the leakage current through an isolation region is to replace a pn junction with silicon dioxide (SiO 2 ) without the damage caused by implantation. [8][9][10][11][12][13] Silicon-on-insulator (SOI) wafers have been used to fabricate power and high-frequency devices. 14,15) Figure 2(a) shows a cross-sectional image of an SOI wafer.…”

Section: Introductionmentioning

confidence: 99%

Fabrication of silicon on insulator wafer with silicon carbide insulator layer by surface-activated bonding at room temperature

Koga

Kurita

2020

Jpn. J. Appl. Phys.

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We propose a process for the fabrication of a silicon-on-insulator (SOI) wafer with a silicon carbide (SiC) insulator layer by combining plasma-enhanced chemical vapor deposition and surface-activated bonding without thermal stress to obtain sufficient thermal conductivity for self-heating power and high-frequency device applications. The thermal conductivity of the deposited SiC layer is twice that of a silicon dioxide (SiO2) layer, and the breakdown electric field of this layer is 10–11 MV cm−1, the same as that of a SiO2 layer. In addition, the bonding interface between the silicon layer and the deposited SiC insulator layer has no voids or punch-out dislocations. Therefore, the SOI wafer with a SiC layer has high thermal conductivity and breakdown electric field; this SOI wafer and its fabrication process will be important for the realization of next-generation self-heating devices such as power and high-frequency devices.

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Section: Introductionmentioning

confidence: 99%

Fabrication of silicon on insulator wafer with silicon carbide insulator layer by surface-activated bonding at room temperature

Koga

Kurita

2020

Jpn. J. Appl. Phys.

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“…However, the mobility is also affected by stress effect due to shallow trench isolation, (STI). Mechanical stress from STI was found to cause up to 19% variation in 0.18 µm technology SOI device [96] and with the scaling down of CMOS technology, MOSFET characteristics become more sensitive to the device layout pattern [97]. The compressive stress from STI edge affects many device characteristics, for example, carrier mobility, threshold voltage (V th ) and transconductance (g m ).…”

Section: Device Fabrication and Experimental Setupmentioning

confidence: 99%

“…B2. Extraction procedure by the GMLE method for fabricated MOSFET with 0.05 µm gate length at V ds = 0:05 V. [96] In the second difference of logarithm of the drain current (SDL) method [95], the gate voltage for the minimum in the ? 2 (I ds )/?V gs 2 -V gs curve is defined as the threshold voltage.…”

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confidence: 99%

Improved effective channel length extraction method for 0.09-0.13 mm CMOS

Eng¹

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13 µm and 0.1 µm CMOS technology. 4.12 I-V characteristics of two NMOS transistors with the same L drawn but different L eff measured by our modified shift-and-ratio method with a Vgs range from 0.2 to 0.5 V , showing that a higher off current and a higher on current correspond to a smaller L eff measured. 4.13 L eff extracted for different Vgs range for 0.13 µm CMOS technology NMOS transistors. V ds was biased at 0.05 V. 4.14 ∆L extracted for different Vgs range for 0.13 µm CMOS technology PMOS transistors. V ds was biased at 0.05 V. 4.15 (a) Variation of L eff in I on-log I off relationship (b) Variation of DIBL in I on-log I off relationship. 4.16 I on versus DIBL for both NMOS and PMOS transistors 4.17 Logarithm of I off versus DIBL for both NMOS and PMOS transistors 4.18 Plot of L eff vs. I off for NMOS transistors fabricated by 0.11 µm CMOS technology. L eff was extracted by MS&R method (0.1-0.5 V V gs range) and also the capacitance method. (Note: CC is correlation coefficient.) 4.19 Plot of L eff vs. I off for NMOS transistors fabricated by 0.11 µm CMOS technology. L eff was extracted by MS&R method at 3 different V gs ranges and also by the S&R method for one V gs range. (Note: CC is correlation coefficient.) 4.20 Plot of L eff vs. I off for PMOS transistors fabricated by 0.11 µm CMOS technology. L eff was extracted by MS&R method (0.1-0.5 V V gs range) and the capacitance method. (Note: CC is correlation coefficient.) 4.21 Plot of L eff vs. I off for PMOS transistors fabricated by 0.11 µm CMOS technology. L eff was extracted by MS&R method for 3 different V gs ranges and also by the S&R method for one V gs range. (Note: CC is correlation coefficient.) 4.22 Plot of I off vs. L eff for NMOS and PMOS transistors fabricated by 90 nm CMOS technology with L gate of 60nm. L eff was extracted by MS&R method (0.1-0.3 V V gs range), (Note: CC is correlation coefficient.) 4.23 Box plot of the measured FICD against various percentages of BARC over-etch trimming.

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Electrical analysis of external mechanical stress effects in short channel MOSFETs on (001) silicon

Gallon

Reimbold

Ghibaudo

et al. 2004

Solid-State Electronics

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Reduction of STI/active stress on 0.18 μm SOI devices through modification of STI process

Cited by 3 publications

References 2 publications

Fabrication of silicon on insulator wafer with silicon carbide insulator layer by surface-activated bonding at room temperature

Fabrication of silicon on insulator wafer with silicon carbide insulator layer by surface-activated bonding at room temperature

Improved effective channel length extraction method for 0.09-0.13 mm CMOS

Electrical analysis of external mechanical stress effects in short channel MOSFETs on (001) silicon

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