Redundancy for yield enhancement in the 3-D computer

Yung, M.W.; Little, Michael J.; Etchells, R.D.; Nash, J.G.

doi:10.1109/wafer.1989.47538

Cited by 9 publications

(10 citation statements)

References 5 publications

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“…The 3-D computer, designed by Hughes Research Laboratories [108], is a cellular array processor implemented in wafer scale integration technology. The most unique feature of its implementation is its use of stacked wafers.…”

Section: Logic Integrated Circuits With Redundancymentioning

confidence: 99%

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Defect tolerance in VLSI circuits: techniques and yield analysis

1998

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Section: Logic Integrated Circuits With Redundancymentioning

confidence: 99%

“…The (2,4) structure that has been selected for implementation in the 3-D computer is shown in Fig. 13(a) [108]. This floorplan has every spare unit adjacent to the four primary units that it can replace.…”

Section: B Modifying the Floorplanmentioning

confidence: 99%

Defect tolerance in VLSI circuits: techniques and yield analysis

1998

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“…This implies that safe matchings can be found for a number of well-known architectures. For example, this result applies to the fault tolerant binary tree architecture proposed by Hassan and Agarwal [7] and Raghavendra et al [ 141, the interstitial redundancy scheme used in the Hughes 3-D Computer [21], and the 2-D augmented mesh proposed in [ 1 I], among others. We also show that this result is tight in the sense that the safe matching problem is NP-complete when each processor is adjacent to at most three spares.…”

Section: Oftimal Reconfigurationmentioning

confidence: 89%

“…One common way of providing fault tolerance in processor arrays is to augment the array with a set of spare processors that can replace primary processors that become faulty. This approach has been proposed for a number of architectures [2], [lo], [13], [18], [19], [21] and a variety of reconfiguration algorithms for these reconfigurable systems have been studied. It has been observed that in many real-time applications, systems are subject to computational loads that alternate between a strict mode in which the computational load is heavy and severe constraints are imposed on response time, and a reluxed mode in which the computational load is light and the constraints on response time are relaxed sub- stantially [8], [ll].…”

Section: Introduction Dvances In Vlsi and Wsi Technologies Allow In-mentioning

confidence: 99%

Optimal reconfiguration algorithms for real-time fault-tolerant processor arrays

Libeskind-Hadas

Shrivastava²,

Melhem³

et al. 1995

IEEE Trans. Parallel Distrib. Syst.

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Abstract--In this paper we consider the problem of reconfiguring processor arrays subject to computational loads that alternate between two modes. A strict mode is characterized by a heavy computational load and severe constraints on response time while a relaxed mode is characterized by a relatively light computational load and relaxed constraints on response time. In the strict mode, reconfiguration is performed by a distributed local algorithm in order to achieve fast recovery from faults. In the relaxed mode, a global reconfiguration algorithm is used to restore the system to a state that maximizes the probability that future faults occurring in subsequent strict modes will be repairable.Several new results are given for this problem. Efficient reconfiguration algorithms are described for a number of general classes of architectures. These general algorithms obviate the need for architecture-specific algorithms for architectures in these classes. We show that it is unlikely that similar algorithms can be obtained for related classes of architectures since the reconflguration problem for these classes is NP-complete. Finally, a general approximation algorithm is described that can be used for any architecture. Experimental results are given, suggesting that our algorithms are very effective.

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“…We note that a number of well-known architectures have the property that D(X) 5 2. For example, the fault tolerant binary tree architecture proposed by Raghavendra et al [8], the interstitial redundancy scheme used in the Hughes 3-D Computer [12], and the 2-D augmented mesh proposed by Melhem [5] 'Optimal kasignments were obtained by exhaustive search.…”

Section: Algorithmmentioning

confidence: 99%

Efficient bi-level reconfiguration algorithms for fault tolerant arrays

Libeskind-Hadas

Shrivastava²,

Melhem³

et al.

Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

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In this paper we consider the problem of reconfiguring processor arrays subject to computational loads that alternate between two modes. A strict mode is characterized by a heavy computational load and Severe constraints on response time while a relazed mode is characterized by a relatively light computational load and relaxed constraints on response time. In the strict mode, reconfiguration is performed by a distributed local algorithm in order to achieve fast recovery from faults. In the relaxed mode, a global reconfiguration algorithm is used to restore the system to a state that maximizes the probability that future faults occuring in subsequent strict modes will be repairable.Several new results are given for this problem. Efficient reconfiguration algorithms are described for a number of general classes of architectures. These general algorithms obviate the need for architecture-specific algorithms for architectures in these classes. We show that it is unlikely that similar algorithms can be obtained for related classes of architectures since the reconfiguration problem for these classes is NP-complete. Finally, a general approximation algorithm is described that can be used for any architecture. Experimental results are given, suggesting that this algorithm is very effect:lve.

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Redundancy for yield enhancement in the 3-D computer

Cited by 9 publications

References 5 publications

Defect tolerance in VLSI circuits: techniques and yield analysis

Defect tolerance in VLSI circuits: techniques and yield analysis

Optimal reconfiguration algorithms for real-time fault-tolerant processor arrays

Efficient bi-level reconfiguration algorithms for fault tolerant arrays

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