Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1 : 8 demultiplexer, and consumes an extremely low 340 mW of power at 3.3 V, including output buffers. It can realize a full optical receiver when connected to a photo detector/preamplifier front end. The second circuit is a complete multirate optical receiver application-specific integrated circuit (ASIC) that integrates a photo diode, a transimpedance amplifier, a limiting amplifier, a digital clock and data recovery circuit, a 1 : 10 demultiplexer, and the asynchronous-transfer-mode-compatible word synchronization logic. It is the most functionally complex InP HBT optoelectronic integrated circuit reported to date. A custom package has also been developed for this ASIC.Index Terms-Heterojunction bipolar transistor, indium phosphide, optical receiver, optoelectronic integrated circuit.

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