Redundant logarithmic arithmetic

Arnold, Mark G.; Bailey, Thomas A.; Cowles, John; Cupal, J.J.

doi:10.1109/12.57046

Cited by 57 publications

(18 citation statements)

References 24 publications

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“…Notice that, unlike simple SLNS, DLNS does not need a special bit to represent zero exactly, but rather uses X D = J. DLNS has some similarity to redundant LNS [1] and multi-dimensional LNS [22] that involve a definition with addition/subtraction of two exponentials; however unlike those systems, in DLNS one of the exponentials is a constant. The choice of the constant J in (12) is arbitrary; a large negative J restricts the denormal behavior to values close to zero (analogous to IEEE-754); J near 0 makes DLNS like FXNS.…”

Section: Dlns Additionmentioning

confidence: 99%

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The Denormal Logarithmic Number System

Arnold¹,

Collange

2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-Economical hardware often uses a FiXed-point Number System (FXNS), whose constant absolute precision is acceptable for many signal-processing algorithms. The almostconstant relative precision of the more expensive Floating-Point (FP) number system simplifies design, for example, by eliminating worries about FXNS overflow because the range of FP is much larger than FXNS for the same wordsize; however, primitive FP introduces another problem: underflow. The conventional Signed Logarithmic Number System (SLNS) offers similar range and precision as FP with much better performance (in terms of power, speed and area) for multiplication, division, powers and roots. Moderate-precision addition in SLNS uses table lookup with properties similar to FP (including underflow). This paper proposes a new number system, called the Denormal LNS (DLNS), which is a hybrid of the properties of FXNS and SLNS. The inspiration for DLNS comes from the denormal numbers found in IEEE-754 (that provide better, gradual underflow) and the µ-law often used for speech encoding; the novel DLNS circuit here allows arithmetic to be performed directly on such encoded data. The proposed approach allows customizing the range in which gradual underflow occurs. A wide gradual underflow range acts like FXNS; a narrow one acts like SLNS. Simulation of an FFT application illustrates a moderate gradual underflow decreasing bit-switching activity 15% compared to underflowfree SLNS, at the cost of increasing application error by 30%. DLNS reduces switching activity 5% to 20% more than an abruptly-underflowing SLNS with one-half the error. Synthesis shows the novel circuit primarily consists of traditional SLNS addition and subtraction tables, with additional datapaths that allow the novel ALU to act on conventional SLNS as well as DLNS and mixed data, for a worst-case area overhead of 26%.

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Section: Dlns Additionmentioning

confidence: 99%

“…Other values of x in the neighborhood ofx use the same representation. The resulting error can be measured in bits of absolute error (1), or in bits of relative error (2): e a = log 2 |x −x| (1) e r = log 2 x −x x = log 2 |1 − x/x|.…”

Section: Introductionmentioning

confidence: 99%

The Denormal Logarithmic Number System

Arnold¹,

Collange

2013

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors

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“…In this paper, we use the signed-logarithmic representation format similar to [5], which consists of a sign bit and a fixed-point number to record the logarithmic value, shown as follows:…”

Section: Lns Representation and Arithmeticmentioning

confidence: 99%

“…Piecewise polynomial approximations, such as Lagrange interpolation [3] and Chebyshev approximation [4], solve the problem by dividing the input value range into small segments and approximating the value with a different polynomial in each segment. On the other hand, on-line methods (also known as digit-serial or iterative methods) [5], [6], calculate the result digit by digit, with a smaller memory cost but increased delay. Meanwhile, a number of different techniques are also proposed to enhance the design by either improving the accuracy or reducing the resource costs, such as error correction [7], coefficient generation on the fly [3], and function transformations [8], [9].…”

Section: Introductionmentioning

confidence: 99%

Optimizing Logarithmic Arithmetic on FPGAs

Sotiriades

Dollas

2007

15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)

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“…In order to reduce the hardware cost for computing these two functions, many table-reduction techniques have been proposed [2,3]. On the other hand, there also have been computational methods introduced, either to compute [4,5] or to avoid [6,7] these two functions. However, we can expect that the size of the coefficient tables used in these computational methods will increase exponentially.…”

mentioning

confidence: 99%

Performance-improved computation of very large word-length LNS addition/subtraction using signed-digit arithmetic

Chen

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003

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Pipelined computation of very large word-length logarithmic number system (LNS) addition/subtraction requires a lot of hardware and long pipeline latency. This paper proposes a base-e exponential algorithm to simplify the exponential computation and to replace half of the pipeline stages by multiplication-and-accumulate operations. By using this approach, the circuit area and the pipeline latency of the previously proposed 64-bit basic LNS addition/subtraction unit can be reduced by 42.4% and 39.22%, respectively. Based on the base-e exponential algorithm approach, we also develop signed-digit (SD) exponential, SD discretization, and SD on-line logarithmic algorithms to further increase the throughput and to reduce the pipeline latency of the LNS computation. From our synthesis results, the throughput of the 64-bit LNS unit can be increased by 61.9% and the pipeline latency can be reduced by 55.0%, without increasing the hardware cost of the basic LNS unit. The circuit area of the 64-bit hardware-reduced LNS unit is estimated to be only 6.89 times the circuit area of a comparable 64-bit floating-point unit. We conclude that the proposed approaches have significantly improved the performance of the previously proposed LNS unit and have made a significant progress towards the implementation of very large word-length LNS arithmetic.

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Redundant logarithmic arithmetic

Cited by 57 publications

References 24 publications

The Denormal Logarithmic Number System

The Denormal Logarithmic Number System

Optimizing Logarithmic Arithmetic on FPGAs

Performance-improved computation of very large word-length LNS addition/subtraction using signed-digit arithmetic

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