Redundant Via Insertion in Restricted Topology Layouts

McCullen, Kevin

doi:10.1109/isqed.2007.138

Cited by 19 publications

(6 citation statements)

References 13 publications

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“…In addition, the modification will not alter the lengths of the critical nets, if we add linear constraints to control the critical wire lengths. The flexible MILP model also allows integrating with a variety of practical issues such as redundant via insertion [10].…”

Section: Discussionmentioning

confidence: 99%

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An MILP-based wire spreading algorithm for PSM-aware layout modification

Tsai¹,

Lin²,

Wang³

2008

2008 Asia and South Pacific Design Automation Conference

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Abstr actPhase shifting mask (PSM) is a promising resolution enhancement technique, which is used in the deep sub-wavelength lithography of the VLSI fabrication process. However, applying the PSM technique requires the layout to be free of phase conflicts. In this paper, we present a mixed integer linear programming (MILP) based layout modification algorithm which solves the phase conflict problem by wire spreading. Unlike existing layout modification methods which first solve the phase conflict problem by removing edges from the layout-associated conflict graphs and then try to revise the layout to match the resultant conflict graphs, our algorithm simultaneously considers the phase conflict problem and the feasibility of modifying the layout. The experimental results indicate that without increasing the chip size, the phase conflict problem can be well tackled with minimal perturbation to the layout. I. Intr oductionOptical lithography has been a critical step in the VLSI fabrication process. As the pitches of leading-edge products scale down, phase shifting mask (PSM) and immersion lithography are viewed as potential solutions to carry the 193nm lithography beyond 65nm node. The key of immersion lithography lies on high-index fluids which increase the numerical apertures of the lithography system. Nevertheless, ASML and Nikon recently announced that the numerical apertures had essentially reached their limit for waterbased immersion lithography [1]. In the 45nm technology node, the pitch of metal 1 (M1) is reduced to 90nm, which necessitates the incorporation of immersion lithography and strong PSM techniques such as alternating PSM (altPSM).Assume that the minimum spacing which can be resolved by applying conventional mask is %. Beyond this spacing, strong constructive diffraction effect interferes the imaging of critical features. Applying altPSM extends the limit of resolution to E (=%/2) by destructive interference. However, this resolution improvement can be achieved only if the apertures of two adjacent critical features are assigned to opposite phases. Although altPSM shows great potential in resolution enhancement, a layout must be compliant to the phase assignment constraint. )LJ shows a layout which cannot satisfy the phase assignment constraint. Since spacing between any two of the three rectangular wire segments in )LJ is critical, any two of these features must be in opposite phases. However, no matter what phase we assign to the bottom feature, it will be the same as one of the upper two features. Thus, this layout has the phase conflict problem.Masks can be categorized into dark field masks and bright field masks. The dark field masks are mainly used for metal layers, and the bright field masks are usually used for poly layers. Targeting on the dark field altPSM, McCullen reported routing restrictions that enable the generation of phase-correct layout [2]. Berman HW DO.[3] proposed a graph based algorithm for solving the phase conflict problem. To obtain altPSM compliant layouts, conflict graph...

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Section: Discussionmentioning

confidence: 99%

“…To maintain the orientations of horizontal wire segments, we have constraint (9). To preserve the graph simplicity constraint, we have constraint (10 …”

Section: C-4mentioning

confidence: 99%

An MILP-based wire spreading algorithm for PSM-aware layout modification

Tsai¹,

Lin²,

Wang³

2008

2008 Asia and South Pacific Design Automation Conference

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“…Chen et al [6] demonstrated simultaneous redundant via insertion and via minimization using a bipartite graph method. Mc�ullen presented the wire spreading technique of tuning routmg resources for redundant via insertion in a restricted topological layout [7]. Nevertheless, a low double-via I insertion rate still causes bottlenecks in redundant via insertion, independently of router efficiency because the double-via I insertion rate depends not only on the routing algorithm, but also on the metal I pin accessibility of ceHs.…”

Section: Introductionmentioning

confidence: 99%

Configurable redundant via-aware standard cell design considering multi-via mechanism

Kan

Hong

Chen

et al. 2013

International Symposium on Quality Electronic Design (ISQED)

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�ell designed redundant via-aware standard ceHs (SCs) can mcrease the redundant vial insertion rate in ceH-based designs. However, with conventional methods, manual and visual-based check are required to locate pins and tune geometries in layouts, which can be very time consuming and unreliable. Instead, an O(NlogN) via-aware standard cell optimization algorithm is developed. The proposed method considers various redundant via configurations such as double-via and rectangle-via which effectively increase the redundant via insertion rate for both concurrent routing and post-layout optimization. As a result, the proposed scheme not only addresses the problem of a low vial insertion rate in nanometer regimes, but also demonstrates an efficient automatie layout optimizer for designing standard ceHs. Compared to the conventional standard library, the proposed method saves considerable design effort and time. Experimental results reveal that the proposed method effectively improves the redundant vial insertion rate by a total of 26.3%. KeywordsDesign for manufacturability (DFM), layout, redundant via, standard ceH (SC)

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“…Second, we can create DVs after routing. Post-routing via doubling installs a redundant via (RV) at a place adjacent to an existing via [4]- [9], [11]- [19]. Some commercial tools [5], [20], [21] have provided such capability to their designers.…”

Section: Introductionmentioning

confidence: 99%

“…RV-aware routers only give a marginally better RV insertion rate [14]. In addition to the above two approaches, MaCullen [19] suggested adding jogs (i.e., modifying a route) to the restricted layout topologies for providing more empty space around a via.…”

Section: Introductionmentioning

confidence: 99%

Router and cell library co-development for improving redundant via insertion at pins

Tseng

Chen

Lin

2008

2008 IEEE International Conference on Computer Design

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In this paper we propose a synergetic approach that integrates router design and cell library engineering for improving post-routing via1 (via between M1 and M2) doubling rate at pins. We develop a double-via (DV) aware multilevel router to exploit the via1 doubling possibilities provided to the cells in a conventional as well as a DV-driven cell library. Compared to a non-DV-aware router using a conventional cell library, our approach using a DV-driven library can on average raise via1 doubling rate by 34%, raise total via doubling rate by 11%, reduce the total number of vias by 3%, and reduce the total number of via1s by 8%. All this can be achieved without incurring any performance and area penalties.

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Redundant Via Insertion in Restricted Topology Layouts

Cited by 19 publications

References 13 publications

An MILP-based wire spreading algorithm for PSM-aware layout modification

An MILP-based wire spreading algorithm for PSM-aware layout modification

Configurable redundant via-aware standard cell design considering multi-via mechanism

Router and cell library co-development for improving redundant via insertion at pins

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