ReEP: A Toolset for Generation and Programming of Reconfigurable Datapaths for Event Processing

Gottschling, Philip; Hochberger, Christian

doi:10.1109/ipdpsw.2017.138

Cited by 2 publications

(3 citation statements)

References 18 publications

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“…Our monitoring system is therefore designed to not only evaluate a specific property specification. Instead, it builds on a flexibly and quickly configurable FPGA-based event processing platform described in [13]. We provide a tool chain for mapping TeSSLa specifications to the platform automatically within seconds.…”

Section: Contributionmentioning

confidence: 99%

“…Long FPGA-synthesis time, however, would render the interactive RETOM workflow impossible in which TeSSLA specifications are adapted frequently. To overcome this problem, we follow [13] by merging several CDFGs into one super CDFG with reconfiguration capabilities. Now the monitoring system consists of multiple instances of the same reconfigurable DP, which can implement at least all of the previously specified monitors.…”

Section: Merging Data Flow Graphsmentioning

confidence: 99%

“…The input CDFG does not necessarily need to be a CDFG of the merging set. As shown in [13] disjoint problems can be matched on already synthesized datapaths when the required resources are available.…”

Section: Programming Monitorsmentioning

confidence: 99%

See 2 more Smart Citations

Rapidly Adjustable Non-intrusive Online Monitoring for Multi-core Systems

Decker

Gottschling

Hochberger

et al. 2017

Lecture Notes in Computer Science

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Abstract. This paper presents an approach for rapidly adjustable embedded trace online monitoring of multi-core systems, called RETOM. Today, most commercial multi-core SoCs provide accurate runtime information through an embedded trace unit without affecting program execution. Available debugging solutions can use it to reconstruct the run offline, but usually for up to a few seconds only. RETOM employs a novel online reconstruction technique that makes the program run available outside the SoC and allows for evaluating a specification formulated in the stream-based specification language TeSSLa in real time. The necessary computing performance is provided by an FPGA-based event processing system. In contrast to other hardware-based runtime verification techniques, changing the specification requires no circuit synthesis and thus seconds rather than minutes or hours. Therefore, iterated testing and property adjustment during development and debugging becomes feasible while preserving the option of arbitrarily extending observation time, which may be necessary to detect rarely occurring errors. Experiments show the feasibility of the approach.

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Section: Contributionmentioning

confidence: 99%

Section: Merging Data Flow Graphsmentioning

confidence: 99%