Refactoring for Data Locality

Beyls, Kristof; D’Hollander, Erik H.

doi:10.1109/mc.2009.57

Cited by 60 publications

(38 citation statements)

References 7 publications

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“…Traditionally, loop transformation is performed by skilled programmers or tuners [5]. Even in a typical profile-driven Copyright c 2014 The Institute of Electronics, Information and Communication Engineers performance tuning process by programmers, detecting hot spots and understanding their loop structures without reading code carefully are known to be helpful for them [6]. Our precise results that show precise loop nest structures and their weights in the execution help make better strategies for loop transformation.…”

Section: Introductionmentioning

confidence: 88%

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Identifying Program Loop Nesting Structures during Execution of Machine Code

Sato

Inoguchi

Nakamura

2014

IEICE Trans. Inf. & Syst.

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SUMMARYThis paper presents a mechanism for detecting dynamic loop and procedure nesting during the actual program execution on-the-fly. This mechanism aims primarily at making better strategies for performance tuning or parallelization. Using a pre-compiled application executable machine code as an input, our mechanism statically generates simple but precise markers that indicate loop entries and loop exits, and dynamically monitors loop nesting that appears during the actual execution together with call context tree. To keep precise loop structures all the time, we monitor the indirect jumps that enter the loop regions and the setjmp/longjmp functions that cause irregular function call transfers. We also present a novel representation called Loop-Call Context Graph that can keep track of inter-procedural loop nests. We implement our mechanism and evaluate it using SPEC CPU2006 benchmark suite. The results confirm that our mechanism can successfully reveal the precise inter-procedural loop nest structures from all of SPEC CPU2006 benchmark executions without any particular compiler support. The results also show that it can reduce runtime loop detection overheads compared with the existing loop profiling method. key words: dynamic loop nests, loop-call context tree, on-the-fly loop detection

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Section: Introductionmentioning

confidence: 88%

“…There are three significant advantages of our loop nest detection system over the previous methods [6]- [8]. The first is that it enables precise detection of inter-procedural dynamic loop nests.…”

Section: Introductionmentioning

confidence: 99%

Identifying Program Loop Nesting Structures during Execution of Machine Code

Sato

Inoguchi

Nakamura

2014

IEICE Trans. Inf. & Syst.

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“…The SLO [7] reuse profiling tool is used to compare the original schedule of Listing 1, with the optimized schedules of Table I. The results are depicted in Figure 11, for the original iteration order the external communications are reduced when a new loop level fits in the buffer.…”

Section: Experimental Evaluationmentioning

confidence: 99%

“…We estimated the energy of data transfer for varying onchip memory size with a memory tracing tool [7], and did energy estimation for external [8] and on-chip [9] accesses. From the result, depicted in Figure 1, we conclude that increasing accelerator utilization with more external memory bandwidth is bad for energy.…”

Section: Introductionmentioning

confidence: 99%

Memory-centric accelerator design for Convolutional Neural Networks

Peemen

Setio

Mesman

et al. 2013

2013 IEEE 31st International Conference on Computer Design (ICCD)

288

153

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Abstract-In the near future, cameras will be used everywhere as flexible sensors for numerous applications. For mobility and privacy reasons, the required image processing should be local on embedded computer platforms with performance requirements and energy constraints. Dedicated acceleration of Convolutional Neural Networks (CNN) can achieve these targets with enough flexibility to perform multiple vision tasks. A challenging problem for the design of efficient accelerators is the limited amount of external memory bandwidth. We show that the effects of the memory bottleneck can be reduced by a flexible memory hierarchy that supports the complex data access patterns in CNN workload. The efficiency of the on-chip memories is maximized by our scheduler that uses tiling to optimize for data locality. Our design flow ensures that on-chip memory size is minimized, which reduces area and energy usage. The design flow is evaluated by a High Level Synthesis implementation on a Virtex 6 FPGA board. Compared to accelerators with standard scratchpad memories the FPGA resources can be reduced up to 13x while maintaining the same performance. Alternatively, when the same amount of FPGA resources is used our accelerators are up to 11x faster.

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“…For simplicity the result matrix C is initialized to 0, and the loop bounds are set to: Bi=500, Bj=400, Bk=300. We used Suggestions for Locality Optimizations (SLO) [17] to simulate the remaining data transfers. Remaining transfers are defined as the total number of memory accesses minus the reuses of data elements, as depicted for different buffer sizes in fig.…”

Section: Motivation: Scheduling For Data Localitymentioning

confidence: 99%

Inter-Tile Reuse Optimization Applied to Bandwidth Constrained Embedded Accelerators

Peemen

Mesman

Corporaal

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-The adoption of High-Level Synthesis (HLS) tools has significantly reduced accelerator design time. A complex scaling problem that remains is the data transfer bottleneck. To scale-up performance accelerators require huge amounts of data, and are often limited by interconnect resources. In addition, the energy spent by the accelerator is often dominated by the transfer of data, either in the form of memory references or data movement on interconnect. In this paper we drastically reduce accelerator communication by exploration of computation reordering and local buffer usage. Consequently, we present a new analytical methodology to optimize nested loops for intertile data reuse with loop transformations like interchange and tiling. We focus on embedded accelerators that can be used in a multi-accelerator System on Chip (SoC), so performance, area, and energy are key in this exploration. 1) On three common embedded applications in the image/video processing domain (demosaicing, block matching, object detection), we show that our methodology reduces data movement up to 2.1x compared to the best case of intra-tile optimization. 2) We demonstrate that our small accelerators (1-3% FPGA resources) can boost a simple MicroBlaze soft-core to the performance level of a high-end Inteli7 processor.

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Refactoring for Data Locality

Cited by 60 publications

References 7 publications

Identifying Program Loop Nesting Structures during Execution of Machine Code

Identifying Program Loop Nesting Structures during Execution of Machine Code

Memory-centric accelerator design for Convolutional Neural Networks

Inter-Tile Reuse Optimization Applied to Bandwidth Constrained Embedded Accelerators

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