Reference Power Supply Connection Scheme for Low-Power CMOS Image Sensors Based on Incremental Sigma-Delta Converters

Abstract

Modern Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, aimed to target low-noise and fast digital outputs, are fundamentally based on column-parallel structures, jointly designed with oversampling column converters. The typical choice for the employed column converters is the incremental sigma-delta structures, which intrinsically perform the correlated multiple sampling, creating an averaging effect over the system thermal noise when used in conjunction with 4T-pinned pixels. However, these types of column converters are known to be power-hungry, especially if the imaging device needs to target high frame rate levels as well. In this sense, the aim of this paper was to address the excess of power dissipation problem that arises from image sensors while employing oversampling high-order incremental converters, by means of using a different connection scheme to supply and to drive the required reference signals across the image sensor on-chip column converters. The proposed connection scheme revealed to be fully functional with no unwanted artifacts in the imager output response, allowing it to avoid 20% to 50% of the power dissipation, relative to the classical on-chip references generation and driving method. Furthermore, this solution allows for a much less complicated and less crowded printed circuit board (PCB) system.

Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

“…This paper expands and deepens the research works from the same authors, presented at the ICEA workshop in 2019 [1], complemented with the research work published in the Sensors and Actuators (S&A) A: Physical Journal in the course of 2020 [2], with the research paper published in the MDPI Electronics Journal published during 2021 [3], in conjunction with the work published in the Microelectronics Journal during 2021 [4]. All these works are concerned with high-order Incremental Signal-Delta (ISD) converters and a low-power design.…”

“…This does not take into account, however, the additional 500 µW of power consumption (per column) that is required and reserved for the on-chip power-hungry ADCs references drivers. Since the per-column total power consumption lies in the order of 1 mW, which is a concern for the driven experiment, which is meant for practical and commercial devices, then the solution for the power saving (relative to the ADC references generation) is proposed in Freitas et al [3]. The power saving amount lies in the order of 50%, by delegating the references generation to the off-chip.…”

“…The downside of the fabricated test chip is that the produced temporal noise was significant, namely for a CIS development that was supposed to be one-step away from a sub-electron solution. In any case, while the test chip was under development, Design-For-Testability (DFT) countermeasures were added [3], to perform additional tests on the on-chip column circuits. Therefore, important conclusions in terms of the circuits' adoption for future CIS designs [4] can be noted, so that sub-electron noise performance can be reached, while maintaining the positive features of the legacy CIS implementation.…”

“…With respect to avoiding excessive power consumption, such as the chip thermal dissipation and the high dark-current related issues (if thermal management is not properly handled), the ADCs references' drivers should be moved off-chip, as stated by Freitas et al [3]-all the while maintaining the correct system functionality through a cost-effective external references generation, supply and driving implementation. 6.…”

A Review of Optical Sensors in CMOS

“…Despite CMOS imagers presenting lower power consumption, this key issue is often overlooked. A work dedicated to this issue and a solution for optimum power consumption was proposed by Freitas et al [76].…”