2013
DOI: 10.1049/el.2013.1010
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Reference spur suppression technique using ratioed current charge pump

Abstract: Reference spurs are one of the main problems in integer-N phaselocked loops (PLLs). A ratioed current charge pump is proposed to suppress reference spur magnitude in the PLL output. The ratioed current charge pump can be implemented by resizing the source and drain network of the charge pump. A formula to calculate the ratioed current and transistor size is presented. The reference spur magnitude for a PLL with a ratioed current charge pump is compared to a conventional charge pump PLL, resulting in about 4 dB… Show more

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Cited by 8 publications
(5 citation statements)
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“…The schematic of basic charge pump is shown in Fig. 1 [27,28]. However, in locked state, the UP and DN signal are periodic narrow pulse with small hold time which are used as the charge and discharge switches respectively [29,30,31].…”
Section: Operation Principles Of the Proposed Dci-cpmentioning
confidence: 99%
“…The schematic of basic charge pump is shown in Fig. 1 [27,28]. However, in locked state, the UP and DN signal are periodic narrow pulse with small hold time which are used as the charge and discharge switches respectively [29,30,31].…”
Section: Operation Principles Of the Proposed Dci-cpmentioning
confidence: 99%
“…Reference spur for the PLL is determined analytically using the simulated value of leakage current. Leakage current, which enters or exits the loop filter when both UP and DN switches are OFF, is found to be 12 nA and hence the phase offset could be determined as [19] ϕ e = 2π × I leak I CP (13) Moreover, the reference spur could be expressed as [19][20][21]…”
Section: Loop Bw Phase Margin Reference Spur and Step Response Of Pllmentioning
confidence: 99%
“…Reference spur for the PLL is determined analytically using the simulated value of leakage current. Leakage current, which enters or exits the loop filter when both UP and DN switches are OFF, is found to be 12 nA and hence the phase offset could be determined as [19] ϕe=2π×IleakICP Moreover, the reference spur could be expressed as [19–21] Pr=20thinmathspacelog][NϕefLBWfref220thinmathspacelog][freffpl where fref (20 MHz) is the input reference frequency, fLBW (900 kHz) is the loop BW, fpl (2.46 MHz) is the pole frequency in the loop filter and N (128) is the division value. The value of reference spur calculated using (14) is found to be −72.02 dBc.…”
Section: Loop Bw Phase Margin Reference Spur and Step Response Of Pllmentioning
confidence: 99%
“…This will result in the reference spur in the PLL output spectrum. Various design techniques have been proposed to directly improve the current matching [1,2,3,4,5,6,7,8,9,10,11,12] or to detect the current mismatch and then apply analog [13,14,15,16,17] or digital [18,19,20,21,22] calibration. The digital calibration technique [20] with a signed counter calibrates the current mismatch of CP by detecting the variation of steady-state phase offset and then changing the amplitude of CP charge or discharge current.…”
Section: Introductionmentioning
confidence: 99%