“…This will result in the reference spur in the PLL output spectrum. Various design techniques have been proposed to directly improve the current matching [1,2,3,4,5,6,7,8,9,10,11,12] or to detect the current mismatch and then apply analog [13,14,15,16,17] or digital [18,19,20,21,22] calibration. The digital calibration technique [20] with a signed counter calibrates the current mismatch of CP by detecting the variation of steady-state phase offset and then changing the amplitude of CP charge or discharge current.…”