Internet of Things (IoT) has been implemented in most advance technologies as part of the emerging 4th industrial revolution, and recently, blockchain technology is being welcomed. These rapid growing technologies giving a big challenge to the students. As such, learning these new technologies should be made easy and simple. However, current education does not specifically offer a curriculum to empower skills and knowledge in IoT and blockchain technology. The aim of this research is to develop learning kit that can provide suitable training to understand concept of IoT and blockchain technology. The kit consists of three parts namely “brain”, “muscle” and “cloud”. Raspberry Pi is used as “brain” of operation that will be interact with the Caiser Cloud platform. A testbox operates as “muscle” to provide simple data input. The input from testbox will be sent, stored and displayed on a platform created using Xojo software. The results show that the learning kit is successfully interact with Caiser Cloud platform and can be used as a training tools for education purpose.

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This paper discusses the effectiveness of the early evaluation questions conducted to determine the academic ability of the new students in the Department of Electrical, Electronics and Systems Engineering. Questions designed are knowledge based -on what the students have learned during their pre-university level. The results show students have weak basic knowledge and this is in contrast to the results obtained during the application for admission to Year 1 of university. Thus, early evaluation questions were implemented to see the relevance in assessing the student's ability, obtained by the use of Rasch analysis, WinSteps. The findings show that the initial assessment is an effective and appropriate method to assess the ability of students, where the Cronbach-α is 0.69 and achieve the acceptable ranges of PT-Measure, Mean Square Outfit or Outfit Mean Square (MNSQ) and z-standardized values ZSTD) Outfit. This shows that Rasch analysis can be used to classify the questions and the students according to their performance level accurately and thus, reveal the true level of the students' ability, despite the small number of samples.

Modern Radio Frequency (RF) transceivers cannot be imagined without high-performance (Transmit/ Receive) T/R switch. Available T/R switches suffer mainly due to the lack of good trade-off among the performance parameters, where high isolation and low insertion loss are very essential. In this study, a T/R switch with high isolation and low insertion loss performance has been designed by using Silterra 0.13µm CMOS process for 2.4GHz ISM band RF transceivers. Transistor aspect ratio optimization, proper gate bias resistance, resistive body floating and active inductor-based parallel resonance techniques have been implemented to achieve better trade-off. The proposed T/R switch exhibits 0.85dB insertion loss and 45.17dB isolation in both transmit and receive modes. Moreover, it shows very competitive values of power handling capability (P1dB) and linearity (IIP3) which are 11.35dBm and 19.60dBm, respectively. Due to avoiding bulky inductor and capacitor, the proposed active inductor-based T/R switch became highly compact occupying only 0.003mm 2 of silicon space; which will further trim down the total cost of the transceiver. Therefore, the proposed active inductor-based T/R switch in 0.13µm CMOS process will be highly useful for the electronic industries where low-power, high-performance and compactness of devices are the crucial concerns.

Reference spurs are one of the main problems in integer-N phaselocked loops (PLLs). A ratioed current charge pump is proposed to suppress reference spur magnitude in the PLL output. The ratioed current charge pump can be implemented by resizing the source and drain network of the charge pump. A formula to calculate the ratioed current and transistor size is presented. The reference spur magnitude for a PLL with a ratioed current charge pump is compared to a conventional charge pump PLL, resulting in about 4 dBc/Hz improvement in the reference spur magnitude.Introduction: Reference spurs are mainly caused by the phase/frequency detector (PFD) and charge pump (CP) circuit non-idealities, namely CP current mismatch, PFD delay, CP switching delay, CP current rise and fall time characteristics, and CP current leakage. These non-idealities cause a periodic ripple in the tuning voltage of a voltage-controlled oscillator (VCO), resulting in spurs at multiple reference frequency offsets from the carrier signal.Several approaches have been carried out to suppress reference spurs in the phase-locked loop (PLL) output. One of these techniques involves lowering the VCO gain, while maintaining a wide VCO output frequency range [1, 2]. These techniques require a complex circuit design and modification of the PLL architecture. Another technique involves minimising the CP current mismatch and minimising the CP current leakage. Minimising CP current mismatch can be implemented by using a gain boosting circuit [3,4] or a calibrated CP [5,6]. Meanwhile, minimising the current leakage can be implemented by using a leakage current compensation circuit [7]. However, although CP current is matched, reference spurs still exist because of other circuit non-idealities such as switching delay. In this Letter, we propose a ratioed current CP to improve reference spur suppression. The ratioed current minimises the voltage ripple on the VCO tuning voltage that is caused by CP current mismatch, PFD delay and switching delay. In the following analysis we use the long-channel transistor model. The same analysis can also be applied for short-channel devices.