Refinement-Based Formal Verification of Asynchronous Wrappers for Independently Clocked Domains in Systems on Chip

Abstract

Abstract. In this paper we propose a novel refinement-based technique to formally verify data transfer in an asynchronous timing framework. Novel data transfer models are proposed to represent data communication between two locally independent clock domains. As a case study, we apply our technique to verify data transfer in a previously published architecture for globally asynchronous locally synchronous on-chip systems. In this case study, we find several race conditions, hazards, and other dangers that were not mentioned in the original publication, and we find additional delay constraints that avoid some of the detected dangers.

Hazard Detection in a GALS Wrapper: A Case Study

“…In the end the model is transformed into a hazard-free representation (see [2]). In a different approach, the authors of [5] successfully verified a GALS system by use of a verification framework, called process spaces. A process considers the set of all possible executions, but without referring to their structural details.…”