Reflectivity-induced variation in implant layer lithography

Bailey, Todd; McIntyre, Greg; Zhang, Bidan; Deschner, Ryan; Mehta, Sohan Singh; Song, Won Joon; Lee, Hyung-Rae; Hue, Yu; Brodsky, Maryjane

doi:10.1117/12.773102

Cited by 12 publications

(7 citation statements)

References 4 publications

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“…For example, bias pulsing offers the ability for higher selectivity improved better loading control, and reduce the aspect ratio dependence in etch, in contrast to a continuous wave plasma only [2][3].…”

Section: Benefit Of Bias Pulsingmentioning

confidence: 99%

Effects of bias RF pulsing plasma in implant layer BARC etch process

Wang¹,

Zhang²,

Shan³

et al. 2016

2016 China Semiconductor Technology International Conference (CSTIC)

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ArF photoresist (PR) and BARC together are being adopted as a LDD (lightly doped drain) implantation blocking layer for applications with smaller CD and larger aspect ratio. BARC open process is followed by a plasma etch process. In this work, the BARC open etch process was performed using a commercial etch system equipped with bias pulsed plasma. The effects of continuous wave (CW) and bias RF pulsed plasma on the BARC open process were studied, and the mechanism was analyzed. Bias pulsed plasma was shown to be effective in improving PR remaining and PR/BARC profile.

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Section: Benefit Of Bias Pulsingmentioning

confidence: 99%

Effects of bias RF pulsing plasma in implant layer BARC etch process

Wang¹,

Zhang²,

Shan³

et al. 2016

2016 China Semiconductor Technology International Conference (CSTIC)

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“…And a previous work showed one of ArF resists with dBARC could get dramatic improvement in CD distributions on a topography wafer, comparing to a TARC process. 1 The paper also cited that CD budgets could be reduced by controlling the reflectivity, thus dBARC process could be one of the solutions on it. In recent years, dBARC process has also been evaluated on HK/MG module to simplify a process scheme for 32nm and future logic devices, as this material has been thought to work as an adhesion promoter between a resist and the dielectric capping films underneath.…”

Section: Introductionmentioning

confidence: 96%

“…As part of the efforts, an evaluation of ArF lithography and its implementation as a new block imaging approach have been successfully performed, and new ArF resists have been under development to meet the aggressive device requirements. 1,3 There are typically many implant levels required to tailor the electrical characteristics of various different devices in a chip, which are used to define the wells, source and drain, halo and extension, and the threshold voltage adjusts (V th ). All lithography processes listed above need to land a resist edge between n-FET and p-FET, to ensure the dopants to be implanted properly where needed and be blocked where not needed.…”

Section: Introductionmentioning

confidence: 99%

Message to the undecided: using DUV dBARC for 32 nm node implants

Lee

Popova²,

Rolick³

et al. 2009

Advances in Resist Materials and Processing Technology XXVI

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In recent years, implant (block) level lithography has been transformed from being widely viewed as non-critical into one of the forefronts of material development. Ever-increasing list of substrates, coatings and films in the underlying stack clearly dictates the need for new materials and increased attention to this challenging area. Control of the substrate reflectivity and critical dimension (CD) on topography has become one of the key challenges for block level lithography and is required in order to meet their aggressive requirements for developing 32nm technology and beyond.The simulation results of wet-developable bottom anti-reflective coating (dBARC) show better reflectivity control on topography than the conventional top anti-reflective materials (TARCs), and make a convincing statement as to viability of dBARC as a working solution for block level lithography. 1 Wet-developable BARC by definition offers substrate reflectivity and resist adhesion control, however there is a need to better understand the fundamental limitations of the dBARC process in comparison to the TARC process. In addition, some specific niche dBARC applications as facilitating adhesion to challenging substrates, such as capping layers in the high-k metal gate (HK/MG) stack, can also be envisioned as most imminent dBARC applications. 2 However, most of the engineering community is still indecisive to use dBARC in production, bound by uncertainties of the robustness and lack of experience using dBARC in production.This work is designed to inspire more confidence in the potential use of this technology. Its objective is to describe testing of one of dBARC materials, which is not a photosensitive type, and its implementation on 32nm logic devices. The comparison between dBARC and TARC processes evaluates impacts of dBARC use in the lithographic process, with special attention to OPC behavior and reflectivity for controlling CD uniformity. This work also shows advantages and future challenges of dBARC process with several 248nm and 193nm resists on integrated wafers, which have shallow trench isolation (STI) and poly gate pattern topography.

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“…Unfortunately, BARC is not favorable in the implant lithography process due to the potential substrate damage resulted from the dry plasma etch, as well as the process complexity and high cost of ownership. With BARC being out of scope, the wafer topography, including the shallow trench isolation (STI) and the poly gate, presents a serious challenge to process control of the implant layer patterning [1,2] . In the implant lithography process, the STI structure will cause the substrate optical reflection and the poly gate will generate the substrate optical diffraction, both of which may lead to the unwanted irradiation in the targeted resist pattern.…”

Section: Introductionmentioning

confidence: 99%

A novel method to reduce wafer topography effect for implant lithography process

Yuan

Bae

et al. 2010

SPIE Proceedings

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Wafer topography structures in the implant lithography process, which include the shallow trench isolation and the poly gate, can result into a severe degradation of the resist profile and significant critical dimension variation. While bottom anti-reflective coating (BARC) is not suitable for the implant lithography because of the plasma induced substrate damage, developable bottom anti-reflective coating (DBARC) is now the most promising solution to eliminate wafer topography effects for the implant layer lithography. Currently, some challenges still remain to be solved and DBARC is not ready for mass production yet. In this study, a novel method is proposed to improve wafer topography effects by use of sub-resolution features. Compared with DBARC, this new approach is much more cost effective. Numerical study by use of Sentaurus-Litho simulation tool shows that the new method is promising and deserves more comprehensive investigation.

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Reflectivity-induced variation in implant layer lithography

Cited by 12 publications

References 4 publications

Effects of bias RF pulsing plasma in implant layer BARC etch process

Effects of bias RF pulsing plasma in implant layer BARC etch process

Message to the undecided: using DUV dBARC for 32 nm node implants

A novel method to reduce wafer topography effect for implant lithography process

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