Register renaming and scheduling for dynamic execution of predicated code

Wang, P.H.; Wang, Hong; Kling, Ralph; Ramakrishnan, K. R.; Shen, John Paul

doi:10.1109/hpca.2001.903248

Cited by 29 publications

(48 citation statements)

References 4 publications

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“…The simulator also models in detail a 144 KB sized PEP-PA branch predictor with 14-bit local history, as described in [21]. This predictor was proposed for an in-order processor and it correlates consecutive predicate definitions with the same logical register name.…”

Section: Methodsmentioning

confidence: 99%

Improving Branch Prediction and Predicated Execution in Out-of-Order Processors

Quiñones

Parcerisa

González

2007

2007 IEEE 13th International Symposium on High Performance Computer Architecture

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If-conversion is a compiler technique that reduces the misprediction penalties caused by hard-to-predict branches, transforming control dependencies into data dependencies. Although it is globally beneficial, it has a negative side-effect because the removal of branches eliminates useful correlation information necessary for conventional branch predictors. The remaining branches may become harder to predict. However; in predicated ISAs with a compare-branch model, the correlation information not only resides in branches, but also in compare instructions that compute their guarding predicates. When a branch is removed, its correlation information is still available in its compare instruction.We propose a branch prediction scheme based on predicate prediction. It has three advantages: First, since the prediction is not done on a branch basis but on a predicate define basis, branch removal after if-conversion does not lose any correlation information, so accuracy is not degraded. Second, the mechanism we propose permits using the computed value ofthe branch predicate when available, instead of the predicted value, thus effectively achieving 100% accuracy on such early-resolved branches. Third, as shown in previous work, the selective predicate prediction is a very effective technique to implement if-conversion on outof-order processors, since it avoids the problem of multiple register definitions and reduces the unnecessary resource consumption ofnullified instructions. Hence, our approach enables a very efficient implementation of if-conversion for an out-of-order processor; with almost no additional hardware cost, because the same hardware is used to predict the predicates of if-converted code and to predict branches without accuracy degradation.

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Section: Methodsmentioning

confidence: 99%

Improving Branch Prediction and Predicated Execution in Out-of-Order Processors

Quiñones

Parcerisa

González

2007

2007 IEEE 13th International Symposium on High Performance Computer Architecture

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“…[20] recognized that multiple definitions would be a problem in the renaming stage of an out-of-order implementation of IA64. The renaming stage is used to give each definition of an architectural register a unique physical name (removing WAW and WAR dependencies).…”

Section: Prior Hardware Solution For Multiple Definition Problemmentioning

confidence: 99%

“…In addition, we compare predicate prediction to Wang et.al. [20] and the most recent work in this area. Section 6 summarizes our paper.…”

Section: Introductionmentioning

confidence: 99%

Predicate prediction for efficient out-of-order execution

Chuang

Calder

2003

Proceedings of the 17th Annual International Conference on Supercomputing

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“…Note that some proposed processor architectures supporting predication may also inject "multiplexor" micro-operations [47], which will incur a run-time cost. (This is also true of the "conditional move" instructions.…”

Section: Synchronization Overheadmentioning

confidence: 99%

Dataflow: A Complement to Superscalar

Budiu

Artigas

Goldstein

2005

IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005.

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There has been a resurgence of interest in dataflow architectures, because of their potential for exploiting parallelism with low overhead. In this paper we analyze the performance of a class of static dataflow machines on integer media and control-intensive programs and we explain why a dataflow machine, even with unlimited resources, does not always outperform a superscalar processor on general-purpose codes, under the assumption that both machines take the same time to execute basic operations. We compare a program-specific dataflow machine with unlimited parallelism to a superscalar processor running the same program. While the dataflow machines provide very good performance on most data-parallel programs, we show that the dataflow machine cannot always take advantage of the available parallelism. Using the dynamic critical path we investigate the mechanisms used by superscalar processors to provide a performance advantage and their impact on a dataflow model.

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Register renaming and scheduling for dynamic execution of predicated code

Cited by 29 publications

References 4 publications

Improving Branch Prediction and Predicated Execution in Out-of-Order Processors

Improving Branch Prediction and Predicated Execution in Out-of-Order Processors

Predicate prediction for efficient out-of-order execution

Dataflow: A Complement to Superscalar

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