Regular VLSI architectures for multiplication modulo (2/sup n/+1)

Curiger, Andreas; Bonnenberg, H.; Kaeslin, Hubert

doi:10.1109/4.92018

Cited by 53 publications

(23 citation statements)

References 4 publications

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“…These group components operate on pairs of 16-bit subblocks and mix them. The three algebraic operations are: (i) 16-bit XOR, (ii) modulo addition 2 16 and )iii) modulo multiplication 2 16 [8]. The proposed IDEA architecture is illustrated in detail in the following Figure 2.…”

Section: Bulk Encryption Unitmentioning

confidence: 99%

Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security

et al. 2006

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Communication protocols for wireless networks have specified security layers, with high-level encryption strength. The dedicated to security layer of Wireless Application Protocol (WAP), is the Wireless Transport Layer Security (WTLS). In this paper, an efficient architecture for the hardware implementation of WTLS is proposed. The introduced system supports bulk encryption, authentication and data integrity. The proposed architecture operates alternatively for a set of ciphers, IDEA, DES, RSA, D.H., SHA-1 and MD5. It is based on two reconfigurable design units: the Reconfigurable Authentication Unit and the Reconfigurable Integrity Unit. These units operate alternatively for different ciphers and achieve to allocate minimized resources, at the same time. The introduced security system has been implemented in an FPGA device. The supported ciphers performance is compared with previously published works, and it has been proven superior to them, in most of the cases. The system's synthesis results prove that the proposed architecture is a flexible and powerful solution for WTLS integration of today's and future wireless networks. The system can be applied to wireless communications servers and mobile devices also. Finally, the proposed architecture can be used as a powerful security engine, in WAP communication networks, with special security demands.

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Section: Bulk Encryption Unitmentioning

confidence: 99%

Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security

et al. 2006

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“…Various multiplication schemes were defined in Curiger et al (1991). Curiger's design used the multiplication scheme with modulo (2 n + 1) adders in which one of the operands (say X) was in diminished-1 representation proposed in Leibowitz (1976) and another operand was in normal weighted form which can be given as: Zimmermann et al (1994), a new approach was taken to avoid high computation time and area.…”

Section: Various Implementations Of Ideamentioning

confidence: 99%

A Survey on Hardware Implementation of IDEA Cryptosystem

Mukherjee

Sahoo

2011

Information Security Journal: A Global Perspective

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The main goal of hardware implementation of a cryptosystem is to make it compatible for high speed networks. The cryptographic algorithms are very much computationally intensive and to achieve a high speed execution, hardware is necessary. In this paper, various hardware implementations of the IDEA cipher is discussed. The hardware implementation involves both ASIC and FPGA implementations and IDEA has been implemented quite a several times in hardware. But a complete survey of all the previous implementations has not been presented before. In each of these implementations, the focus has been made on the data throughput, area requirements and the architecture of the algorithm proposed.

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“…There has been a lot of academic activity in researching an optimum implementation of the modulo (2 16 + 1) multiplier [12], [13], [14], but the research has been limited to full-custom design.…”

Section: Modulo (2 16 + 1) Multiplicationmentioning

confidence: 99%

6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm

Hämäläinen

Tommiska

Skyttä

2002

Lecture Notes in Computer Science

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Abstract. IDEA (International Data Encryption Algorithm) is one of the strongest secret-key block ciphers. The algorithm processes data in 16-bit subblocks and can be fully pipelined. The implementation of a fully pipelined IDEA algorithm achieves a clock rate of 105.9 MHz on Xilinx' XCV1000E-6BG560 FPGA of the Virtex-E device family. The implementation uses 18105 logic cells and achieves a throughput of 6.78 Gbps with a latency of 132 clock cycles.

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Regular VLSI architectures for multiplication modulo (2/sup n/+1)

Cited by 53 publications

References 4 publications

Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security

Design, Architecture and Performance Evaluation of the Wireless Transport Layer Security

A Survey on Hardware Implementation of IDEA Cryptosystem

6.78 Gigabits per Second Implementation of the IDEA Cryptographic Algorithm

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