Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments

Hassan, Syed Minhaj; Choudhary, Dhruv; Rasquinha, Mitchelle; Yalamanchili, Sudhakar

doi:10.1109/pact.2011.33

Cited by 7 publications

(3 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the same time, Hassan et al [14] suggested that optimizing BLP is more important than improving row buffer hits, even though there is a trade-off.…”

Section: Increasing Ll Hit Ratesmentioning

confidence: 99%

A survey of techniques for warp scheduling in GPUs

Sandokji

Essa

Fadel

2015

2015 IEEE Seventh International Conference on Intelligent Computing and Information Systems (ICICIS)

View full text Add to dashboard Cite

The heterogeneous nature of Graphics processor unit (GPU) -CPU makes it a candidate for coming exascale systems.The cores of GPGPU-which is a cost-effective computing platform-are characterized by long periods of inactive times, which results in the underutilization of the hardware resources. This is due to several factors like the limitation of on-chip memory and register files, the inefficient scheduling mechanisms, and communication bottlenecks GPU -CPU communication. In order to counteract the underutilization of recourses, certain techniques have been proposed. In this research, many architectural and system-level techniques aiming to manage and fully leverage GPU resources are surveyed, compared and evaluated. Also, the significance and challenges of warp scheduler in GPUs are thoroughly discussed. The main purpose of this paper is to provide researchers an insight into warp scheduler techniques for GPUs, as well as motivate them to present more efficient methods for enhance performance via improve thread scheduler in future GPUs.

show abstract

“…In the same time, Hassan et al [14] suggested that optimizing BLP is more important than improving row buffer hits, even though there is a trade-off.…”

Section: Increasing Ll Hit Ratesmentioning

confidence: 99%

A survey of techniques for warp scheduling in GPUs

Sandokji

Essa

Fadel

2015

2015 IEEE Seventh International Conference on Intelligent Computing and Information Systems (ICICIS)

View full text Add to dashboard Cite

show abstract

“…In particular, the work by Hassan et al [13] quantifies the trade-off between BLP and row locality for multi-core systems, and concludes that bank-level parallelism is more important. Our results show that the prefetch-aware warp scheduler, which favors banklevel parallelism, provides higher average performance than the two-level scheduler [34], which favors row buffer locality (but this effect could be due to the characteristics of applications we evaluate).…”

Section: Related Workmentioning

confidence: 99%

Orchestrated scheduling and prefetching for GPGPUs

Jog

Kayıran

Mishra

et al. 2013

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

In this paper, we present techniques that coordinate the thread scheduling and prefetching decisions in a General Purpose Graphics Processing Unit (GPGPU) architecture to better tolerate long memory latencies. We demonstrate that existing warp scheduling policies in GPGPU architectures are unable to effectively incorporate data prefetching. The main reason is that they schedule consecutive warps, which are likely to access nearby cache blocks and thus prefetch accurately for one another, back-to-back in consecutive cycles. This either 1) causes prefetches to be generated by a warp too close to the time their corresponding addresses are actually demanded by another warp, or 2) requires sophisticated prefetcher designs to correctly predict the addresses required by a future "far-ahead" warp while executing the current warp.We propose a new prefetch-aware warp scheduling policy that overcomes these problems. The key idea is to separate in time the scheduling of consecutive warps such that they are not executed back-to-back. We show that this policy not only enables a simple prefetcher to be effective in tolerating memory latencies but also improves memory bank parallelism, even when prefetching is not employed. Experimental evaluations across a diverse set of applications on a 30-core simulated GPGPU platform demonstrate that the prefetch-aware warp scheduler provides 25% and 7% average performance improvement over baselines that employ prefetching in conjunction with, respectively, the commonlyemployed round-robin scheduler or the recently-proposed two-level warp scheduler. Moreover, when prefetching is not employed, the prefetch-aware warp scheduler provides higher performance than both of these baseline schedulers as it better exploits memory bank parallelism.

show abstract

“…Mutlu and Moscibroda [41] describe parallelism-aware batch scheduling, which aims to preserve each thread's BLP in a multi-core system. Hassan et al [18] suggest that optimizing BLP is more important than improving row buffer hits, even though there is a trade-off. Our work uses this observation to focus on enhancing BLP, while restoring the lost row locality by memory-side prefetching.…”

Section: Related Workmentioning

confidence: 99%

Owl

Jog

Kayıran

Nachiappan

et al. 2013

Proceedings of the Eighteenth International Conference on Architectural Support for Programming Languages and Operating Systems

187

View full text Add to dashboard Cite

Emerging GPGPU architectures, along with programming models like CUDA and OpenCL, offer a cost-effective platform for many applications by providing high thread level parallelism at lower energy budgets. Unfortunately, for many general-purpose applications, available hardware resources of a GPGPU are not efficiently utilized, leading to lost opportunity in improving performance. A major cause of this is the inefficiency of current warp scheduling policies in tolerating long memory latencies.In this paper, we identify that the scheduling decisions made by such policies are agnostic to thread-block, or cooperative thread array (CTA), behavior, and as a result inefficient. We present a coordinated CTA-aware scheduling policy that utilizes four schemes to minimize the impact of long memory latencies. The first two schemes, CTA-aware two-level warp scheduling and locality aware warp scheduling, enhance per-core performance by effectively reducing cache contention and improving latency hiding capability. The third scheme, bank-level parallelism aware warp scheduling, improves overall GPGPU performance by enhancing DRAM bank-level parallelism. The fourth scheme employs opportunistic memory-side prefetching to further enhance performance by taking advantage of open DRAM rows. Evaluations on a 28-core GPGPU platform with highly memory-intensive applications indicate that our proposed mechanism can provide 33% average performance improvement compared to the commonly-employed round-robin warp scheduling policy.

show abstract

Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments

Cited by 7 publications

References 1 publication

A survey of techniques for warp scheduling in GPUs

A survey of techniques for warp scheduling in GPUs

Orchestrated scheduling and prefetching for GPGPUs

Owl

Contact Info

Product

Resources

About