Relation Between Morphology, Etch Rate, Surface Wetting, and Electrochemical Characteristics for Micromachined Silicon Subject to Galvanic Corrosion

Abstract

Immersion of silicon in HF-based solutions is utilized in microsystems fabrication to render freestanding mechanical structures. Such etching, however, creates a galvanic couple between silicon and a metallic layer ͑e.g., gold͒, resulting in corrosion damage. Morphology, resistive probe, surface wetting, and electrochemical characterization ͑vs Cu/CuF͒ of single-and polycrystalline silicon subjected to galvanic corrosion in three HF-based solutions ͑undiluted 48% HF, UDHF:H 2 O, and UDHF:Triton X-100͒ are used here to formally substantiate the results of a previous mechanical ͑microtensile͒ study. Porosity estimated from the morphology of corroded samples allows the corrosion current density to be determined from etch-rate measurements, according to Faraday's law. Resistive probe structures are used to simulate the microtensile specimens, thereby characterizing corrosion current as a function of time, etchant type, illumination, and the amount of metal utilized. The measured current density of micromachined silicon is compared against ͑100͒ wafer specimens using polarization characterization, identifying the porous Si formation regime. Using sessile drop measurements, the three etchants are further distinguished based on their surface-wetting characteristics. The chronopotentiometry, resistive probe, and microtensile characterizations all identify the behavior regimes of rapid initiation, subsequent steady-state corrosion, and the final catastrophic failure of the microtensile specimens.

Fracture strength of micro- and nano-scale silicon components

“…The galvanic corrosion argument was later supported by Miller et al, in a detailed analysis of the galvanic couple that forms during etching of Si MEMS with gold metallization layers. 223 The galvanic corrosion process due to etching in 49% HF in the presence of a metallization layer led to the formation of a thick, pitted, surface oxide layer, with preferential attack of the grain boundaries, that caused a precipitous loss of strength, 200 comparable to that reported by Chasiotis and Knauss. 133 However, when the same devices were fabricated without a gold metallization layer there was essentially no loss in r f even after 90 min of exposure to the HF solution.…”

“…As also shown in the Appendix, the compliance values provide a means of estimating the elastic constants of an isotropic polycrystal, E (poly) ¼ 163 GPa and (poly) ¼ 0. 223, and these are shown as the circular dashed lines in Figs. 5(a) and 5(b).…”

Connections between morphological and mechanical evolution during galvanic corrosion of micromachined polycrystalline and monocrystalline silicon

“…9. 42 For example, the porosity P ranged between 20% and 47% for etch times Ͻ60 min, whereas P exceeded 70% for etch times ജ60 min. To observe the pores, which are typically 5 -15 nm in diameter and interspaced by 10-20 nm, a field emission electron gun was required.…”

Stronger silicon for microsystems

“…The etch-induced surface defect structure and oxide thickness of both single-crystal and polycrystalline silicon has been shown to be strongly affected by anodic oxidation/galvanic corrosion when silicon is in intimate contact with a metal layer such as gold [12][13][14][15]. This galvanic corrosion can result in a highly porous, extensively oxidized surface layer, and the extent of surface damage has been shown to correlate well with observed degradation in the fracture strength, which can be reduced by >90% under extreme conditions [16,17].…”