Relative Timing Latch Controller with Significant Improvement on Power, Performance, and Robustness

Tang, Xiqin; Li, Yang; Liu, Wanting; Qiao, Shushan; Zhou, Yumei; Shang, Delong

doi:10.1109/icicm54364.2021.9660250

Cited by 1 publication

(2 citation statements)

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“…The RT asynchronous controller (RTAC) proposed in [13] is designed based on the 4-phase protocol, which is characterized by its high speed and small size. Furthermore, it can be easily synthesized by synchronous EDA tools as it is built with standard cells.…”

Section: The 4-phase Rt Pipelinementioning

confidence: 99%

“…This paper focuses on developing a high-performance asynchronous BD pipeline that is both simple in design and amenable to synthesis. In [13], a small, fast, and synthesizable 4-phase asynchronous controller called RT controller has been introduced and compared with other existing asynchronous controllers. And this work is an extension of the previous work, in this paper, we first built a 4-phase RT pipeline, and the HPSAP pipeline is obtained by converting the 4-phase RT pipeline into a quasi-2phase one with the proposed quasi-2phase conversion method.…”

Section: Introductionmentioning

confidence: 99%

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HPSAP: A High-Performance and Synthesizable Asynchronous Pipeline With Quasi-2phase Conversion Method

Tang,

Wang,

et al. 2023

IEEE Access

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This paper presents a high-performance and synthesizable asynchronous pipeline called HPSAP pipeline. First, a 4-phase pipeline controlled by the relative-timing (RT) controller is designed. The controller is small (7 gates) and its handshake protocol is highly concurrent, resulting in fewer component delays in cycle time. However, the RT pipeline's throughput is limited by the inherent reset phase in the 4-phase protocol. Thus, the variant HPSAP pipeline is proposed with the quasi-2phase conversion method. Unlike other existing solutions which aimed at reducing the reset time of the 4-phase protocol, this method imitates the behavior of the 2-phase pipeline and re-activates the reset edge by two steps: 1) replacing all delay-matched units with the maximum delay; 2) adding a small pulse generator on each RT controller. The post-layout HSPICE simulation of a 4-bit 10-stage HPSAP FIFO indicated a throughput of 5.382 giga data item per second (GDI/s) under SMIC 55nm CMOS technology, which was 77.5% and 14.65% higher than the Click pipeline and Mousetrap pipeline. In the pipeline with processing, a 32×32 bits multiplier was built, and the maximum working frequency of the HPSAP multiplier was faster than Mousetrap and the synchronous counterparts.INDEX TERMS High-performance, asynchronous pipelines, relative-timing, asynchronous controller, 4phase handshake protocol.

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Section: The 4-phase Rt Pipelinementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%