Relaxed Si0.7Ge0.3 layers grown on low-temperature Si buffers with low threading dislocation density

Abstract

Si 0.7 Ge 0.3 epilayers with low threading dislocation density have been grown on Si (001) substrates by introducing a low temperature Si buffer. Such a structure can be used as the buffer for the growth of device structures. In comparison with the conventional compositionally graded buffer system, it has the advantages of having lower threading dislocation density, smaller thickness for required degree of relaxation, and smoother surface. Experimental evidence suggests that an anomalous relaxation mechanism has been involved.

Strain relaxation of thin Si0.6Ge0.4 grown with low-temperature buffers by molecular beam epitaxy

“…This was consistent with the fact that the growth scheme of using LT-Si buffer was usually successful for x Յ 0.3 when the buffer was grown at ϳ400°C. 12,13,17 Experiments by using positron annihilation spectroscopy have proven that a Si layer grown at 400°C contained the highest point defect density. 30 However, a single LT-Si buffer clearly showed a limited capability for enhancing the relaxation of the Si 0.6 Ge 0.4 layer, as revealed in Fig.…”

“…Upon experimental observations, several models of a large diversity have been proposed to address the mechanism of LT buffers for the strainrelaxation enhancement. For example, Li et al 13 speculated that there existed low energy sites in the LT buffer for dislocation nucleation, or that point defects could "trap" propagating dislocations; Kasper et al 14 suggested that the point defects may assist dislocation nucleation at an earlier stage and promote climbing of dislocations, resulting in a higher degree of relaxation with lower densities of threading dislocations; Luo et al 9 further demonstrated that the compliant effect of a LT-Si buffer layer also contributed to the resulted low-defect strain-relaxed SiGe VS with a smooth surface; Vyatkin 16 lately proposed a model based on the atomic rearrangement of atoms and vacancies at the LT-Si/SiGe interface; and some other explanations as well. However, none of those were adequate enough to explain why the LT-buffer growth scheme has been unsuccessful in fabrication of highquality Si 1−x Ge x VSs mainly with 0.4Յ x Ͻ 0.6.…”

“…In the past two decades, a considerable amount of effort has been made trying to solve this problem. Several growth schemes and fabrication techniques were proposed and studied, which included compositionally-graded SiGe growth, 2,7 ion implantation during SiGe growth, 8 incorporation of strain compliant buffer layers, 9,10 post-growth annealing and intermixing, 11 low-temperature ͑LT͒ Si or/and SiGe buffer layers, [12][13][14][15] etc. Among them, the technical approaches based on the concept of point defect injection and interaction with dislocations by using LT growth of a Si or SiGe buffer layer have attracted a large interest due to the simple process and the much lower demanded growth thickness.…”

Strain Relaxation and Induced Defects in SiGe Thin Films Grown on Ion-Implanted Si Substrates

“…For this purpose, a graded buffer method and low-temperature buffer method have been proposed. [5][6][7][8][9] However, those methods have some demerits. In order to form relaxed SiGe by the graded buffer method, 1$2 mm thickness of SiGe is necessary.…”

Hall mobility enhancement caused by annealing of Si0.2Ge0.8/Si0.7Ge0.3/Si(001) p-type modulation-doped heterostructures

“…The Si 0.2 Ge 0.8 channel was grown at T g ϭ300°C on a quite thin ͑850 nm thick͒ virtual substrate involving a low-temperature (T g ϭ390°C) Si buffer. 3,4 The top layers of the VS were relaxed with respect to the lattice constant of the Si 0.7 Ge 0.3 bulk alloy. The active layers of a MOD heterostructure were similar in each sample and consisted of an undoped channel for mobile carriers ͑in this case holes͒, a 7 nm thick undoped spacer layer that separates the ionized dopants from the channel and a 10 nm thick boron doping layer with a doping level of 2ϫ10 18 cm Ϫ3 .…”