Reliability Analysis of Memristor Crossbar Routers: Collisions and On/off Ratio Requirement

Chen, Junren; Wu, Chunsheng; Indiveri, Giacomo; Payvand, Melika

doi:10.1109/icecs202256217.2022.9970901

Cited by 3 publications

References 12 publications

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Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems

Dalgaty,

Moro,

Demirağ

et al. 2024

Nat Commun

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The brain’s connectivity is locally dense and globally sparse, forming a small-world graph—a principle prevalent in the evolution of various species, suggesting a universal solution for efficient information routing. However, current artificial neural network circuit architectures do not fully embrace small-world neural network models. Here, we present the neuromorphic Mosaic: a non-von Neumann systolic architecture employing distributed memristors for in-memory computing and in-memory routing, efficiently implementing small-world graph topologies for Spiking Neural Networks (SNNs). We’ve designed, fabricated, and experimentally demonstrated the Mosaic’s building blocks, using integrated memristors with 130 nm CMOS technology. We show that thanks to enforcing locality in the connectivity, routing efficiency of Mosaic is at least one order of magnitude higher than other SNN hardware platforms. This is while Mosaic achieves a competitive accuracy in a variety of edge benchmarks. Mosaic offers a scalable approach for edge systems based on distributed spike-based computing and in-memory routing.

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Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems

Dalgaty,

Moro,

Demirağ

et al. 2024

Nat Commun

Self Cite

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Scaling Limits of Memristor-Based Routers for Asynchronous Neuromorphic Systems

Chen,

Yang,

et al. 2024

IEEE Trans. Circuits Syst. II

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Non-linear Reconfigurable Threshold Logic Gates Based on Nanostructured Metallic films

Martini,

Paroli,

Milani

2024

Preprint

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The dominion of Boolean logic circuits (BLCs) in current electronic design and synthesis tools is increasingly being called into question by challenges posed by the extreme miniaturization and energy footprint typical of AI applications. Compared to BLCs, Threshold Logic Gates (TLGs), by programming the weights, allow for more than two input states, which can enhance complexity in simplifying circuit design. Memristors organized in crossbar arrays architectures have been proposed to implement the programmable weights of threshold logic elements. An alternative TLG design, called Receptron, has been recently proposed: it is based on nonlinear weights thus widening the spectrum of Boolean computable functions while simplifying training thanks to a random search protocol. Here we present a theoretical and an experimental characterization of the Receptron model to determine the connection between the structure of the weights and function computability, identifying sub-linearity as an enabling feature. These results allowed the fabrication of an improved version of a Receptron device, enhancing its sub-linearity and random search efficiency thanks to an ad hoc circuit. This nonlinear threshold logic gate device can be considered for the integration with other conventional logic components for higher levels of computational complexity. Corresponding authors: paolo.milani@mi.infn.it; bruno.paroli@unimi.it

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Reliability Analysis of Memristor Crossbar Routers: Collisions and On/off Ratio Requirement

Cited by 3 publications

References 12 publications

Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems

Mosaic: in-memory computing and routing for small-world spike-based neuromorphic systems

Scaling Limits of Memristor-Based Routers for Asynchronous Neuromorphic Systems

Non-linear Reconfigurable Threshold Logic Gates Based on Nanostructured Metallic films

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