Reliability and early failure in Cu/oxide dual-damascene interconnects

Abstract

The drive toward greater device density and higher performance in Si-based microelectronics technology has led to the recent transition to newer backend interconnect materials. However, this transition must be accomplished without sacrificing the reliability requirements necessary for long-term product functionality. 1,2 The recent introduction of Cu metallization to replace Al(Cu) technology is one example, 3 but the transition will also later require the incorporation of new and often exotic low-k interlevel and intralevel dielectrics as well as ultrathin Cu DB materials. The rapid introduction of new materials in advanced integrated circuit technology is in marked contrast to the seemingly less turbulent prior history-at least from a materials perspective-in microelectronics. All this materials change will also be done under a new interconnect integration architecture: the single-damascene (SD) and dual-damascene (DD) processes. The impact of these new materials and integration scheme on interconnect reliability, such as electromigration (EM) and stress-induced voiding, is still presently not well understood, and the literature on Cu/low-k reliability is still rather sparse. Yet, the knowledgebase is growing, and certain aspects of the effect of the damascene architecture on at least EM reliability are becoming clearer. DD Interconnects: Basic ArchitectureThe basic layout of a Cu-based, submicron, twolevel interconnect suitable for study of EM phenomena in DD systems is shown in Fig. 1a. The DD interconnect is placed at the upper metal level (M2), while a SD interconnect is used at the lower level metal (M1). The Cu metal is surrounded by a thin Ta diffusion barrier (DB) around its sides and bottom and by a capping layer (CL, typically SiN x ) on top. A typical barrier thickness may range between 100 and 300 Å, but the thickness on the via sidewall may be thinner by, say, 25-50%. The CL thickness is typically in the range of 1000 Å. The specific thickness dimensions of these films may vary depending on the technology node targeted. An intralevel dielectric material (ILD, for example, CVD-based SiO x glass) lies between the metal lines. Both the ILD and CL are targeted as regions where the introduction of new lower-k materials will be necessary for future device performance improvements. The M1 and M2 interconnects are electrically connected through the via V1, which is processed as a continuous part of the M2 interconnect.In EM studies on DD interconnects, two current flow directions must be considered. The first electron Recent results on up-direction electromigration (EM) studies on Cu dual-damascene (DD) interconnects are presented. The issue of the DD process and its potential effect on EM reliability is described with special focus on the peculiarities of the DD interconnect architecture in comparison to the previous subtractively etched Al-based interconnect technology. Experiments performed on multilink, DD interconnects that highlight EM reliability issues, such as early failure, and the Blech effect a...

Statistical Analysis of Electromigration Lifetimes and Void Evolution for Cu Interconnects

“…Furthermore, Figure 6.14 seems to indicate that the distribution corresponding to DD samples deviates from the straight line in the lognormal plot for small percentage values suggesting an early failure population of about 6%. These data points are most likely due to void formation in the via, which requires only a small void to fail the line as discussed in several publications [for instance : Ogawa 2001, Ogawa 2002a, Gill 2002, Lai 2001. However, they prohibit fitting a monomodal distribution to the measured data to obtain the median and sigma values.…”

Effect of improved contact on reliability of sub-60 nm carbon nanotube vias

“…To implement such approaches, the Blech length [23][24][25], or the maximum length of the interconnect line at which the internal stress in the conductor can offset electromigration, is experimentally determined. Interconnect lines are then designed for lengths shorter than the Blech length [24,26,27] to prevent electromigration. In addition, capping layers are employed to cover the interconnect lines so that the conformal coating of such layers can provide an adhesive force for the conductor to counter electromigration.…”