Reliability and Performance of CMOS-Compatible Multi-Level Graphene Interconnects Incorporating Vias

Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

“…The successful growth of highquality MLG on both levels also confirms the applicability of the growth technique on arbitrary surface morphologies. X-ray photoelectron spectroscopy (XPS) analyses of the grown MLG reveal that the exact peak position (1202.3 eV) and atomic composition (∼83%) corresponding to the C = C sp2 bond can also be observed in the conventional CVD grown MLG [25], once again validating the high-quality growth of the solid-phase MLG.…”

“…The amorphous carbon prevents Cu and Ni layers from interdiffusion and aids the graphene growth process by acting as an additional source of readily available carbon at the Cu interface. Excellent optical and material characterizations of the MLG grown on Cu [25] demonstrate the outstanding reliability of the growth technique on metallic substrates.…”

“…Due to the potential use of MLG as a capping layer for conventional Cu interconnects [37], we demonstrate high-quality MLG growth directly on Cu without the need for any transfer process [25]. As both Ni and Cu have finite solubilities at ∼350 • C, a ∼2 nm amorphous carbon layer [25] is inserted between them [ Fig. 3(b)].…”

“…form CMOS-compatible multi-level MLG growth on arbitrary surface topologies and substrates; 2) demonstration of an SE-enabled multi-level MLG/via scheme that is compatible with BEOL process and exhibits < 2% via-resistance change under 200 MA/cm 2 current stress; and 3) scalability analysis of the proposed multi-level MLG interconnect scheme to evaluate its benefits at ultimate scaled dimensions. In this article, we present a much more rigorous evaluation of our recent work [25], by providing more evidence and reasoning behind the nature of our results.…”

“…The major contributions of this work include: 1) demonstration of large-area and uni- (a) Schematic of the initial stack used for growing MLG at 350 • C directly onto SiO 2 using the CMOS-compatible solid-phase growth technique [19]. (b) Schematic of the initial stack used for growing MLG directly on Cu substrates, as demonstrated in [25].…”