Reliability-Aware Training and Performance Modeling for Processing-In-Memory Systems

Sun, Hanbo; Zhu, Zhenhua; Cai, Yi; Zeng, Shulin; Qiu, Kaizhong; Wang, Yu; Yang, Huazhong

doi:10.1145/3394885.3431633

Cited by 2 publications

(1 citation statement)

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“…Networks-on-chip continue playing a central role as manycore processors start dominating the server [1,2] and deep learning [3][4][5] market. As the commercial solutions scale up, the latency, area, and power consumption overheads of NoCs become increasingly crucial.…”

Section: Introductionmentioning

confidence: 99%

Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration

Mandal¹,

Tong²,

Ayoub³

et al. 2021

Preprint

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Fast and accurate performance analysis techniques are essential in early design space exploration and pre-silicon evaluations, including software eco-system development. In particular, on-chip communication continues to play an increasingly important role as the many-core processors scale up. This paper presents the first performance analysis technique that targets networks-on-chip (NoCs) that employ weighted roundrobin (WRR) arbitration. Besides fairness, WRR arbitration provides flexibility in allocating bandwidth proportionally to the importance of the traffic classes, unlike basic round-robin and priority-based arbitration. The proposed approach first estimates the effective service time of the packets in the queue due to WRR arbitration. Then, it uses the effective service time to compute the average waiting time of the packets. Next, we incorporate a decomposition technique to extend the analytical model to handle NoC of any size. The proposed approach achieves less than 5% error while executing real applications and 10% error under challenging synthetic traffic with different burstiness levels.

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Section: Introductionmentioning

confidence: 99%