Reliability challenges accompanied with interconnect downscaling and ultra low-k dielectrics

Abstract

The continuous downscaling of interconnect dimensions in combination with the introduction of porous low-k materials has increased the number of integration challenges tremendously. In this paper, the authors focus mainly on the impact of porous low-k on the interconnect reliability.Numerous reliability issues are induced by the porosity compared to the dense low-k materials. The impact of these mechanically inferior materials on packaging is well known. However, on top of the mechanical reliabiIity, the ultra low-k materials are extremely vulnerable to processing (especially to plasmas), due to their inherent porosity. Additionally, it is difficult to deposit a continuous, thin barrier on the porous low-k interfaces. The inferior properties of porous low-k materials as compared to their dense equivalents are thought to induce numerous reliability issues, which are in addition to the ones caused by the continuous downscaling of metal fines and dielectric spacings, All of this together has an enormous impact on the reliability of the end product. IntroductionDriven by aggressive technology roadmap requirements and diverse application-driven requirements, the 45nm technology node will require substantial technology development and innovation in device structure, front-end and back-end materials and processes, and lithography

Novel integration of ultrathin Al2O3 with low-k dielectric as bilayer liner for capacitance optimization and stress mitigation in Cu through-silicon-via

“…Low-k material with a lower permittivity 14) is known to significantly reduce the CMOS backend interconnect capacitance in deep submicron technology nodes. 15) Low-k material is successfully integrated as the TSV liner to further reduce the accumulation capacitance. Flat-band voltage (V FB ) shift is again achieved by inducing negative fixed charge at the Si=low-k interface with an ultrathin Al 2 O 3 layer so that the TSV operates at stable accumulation capacitance region.…”

“…Flat-band voltage (V FB ) shift is again achieved by inducing negative fixed charge at the Si=low-k interface with an ultrathin Al 2 O 3 layer so that the TSV operates at stable accumulation capacitance region. 13) Moreover, low-k dielectric with a lower elastic modulus 15) can act as a compliant layer to cushion the thermos-mechanical stress from Cu-TSV to the surrounding Si for better reliability.…”

Influence of roughness on the detection of mechanical characteristics of low- k film by the surface acoustic waves

“…This process inevitably results in poor mechanical characteristics, which leads to serious reliability problems and restricts the chemical mechanical polishing (CMP) process of ULSI. [2][3][4] Hence, the good mechanical property of low-k film is essential to realize the application of lowk film in the advanced metallization system. Therefore, the accurate Young's modulus determination method for low-k film is highly desired.…”

Through Silicon Via Fabrication with Low-κ Dielectric Liner and Its Implications on Parasitic Capacitance and Leakage Current

“…Lowdielectric can significantly reduce the complementary metaloxide-semiconductor (CMOS) backend interconnect capacitance and provide many advantages in circuit performances in deep submicron technology nodes. 5) Since low-dielectric and process is compatible with TSV process, it can be used in principle to reduce TSV capacitance. In this work, TSV with low-material as the liner is successfully fabricated.…”