Reliability consideration for advanced microelectronics

Kayali, S.

doi:10.1109/prdc.2000.897290

Cited by 6 publications

(4 citation statements)

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“…Soft errors are transient faults caused due to multiple sources like static noise, external interference, and so forth, but the predominant cause of soft errors in modern processors is charge carrying radiation particles. In the era of many core systems the failure rate of our computing systems due to soft errors has exponentially increased, to reach critical levels [21].…”

Section: Introductionmentioning

confidence: 99%

Control Flow Checking or Not? (for Soft Errors)

Rhisheekesan

Jeyapaul

Shrivastava

2019

ACM Trans. Embed. Comput. Syst.

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Huge leaps in performance and power improvements of computing systems are driven by rapid technology scaling, but technology scaling has also rendered computing systems susceptible to soft errors. Among the soft error protection techniques, Control Flow Checking (CFC) based techniques have gained a reputation of being lightweight yet effective. The main idea behind CFCs is to check if the program is executing the instructions in the right order. In order to validate the protection claims of existing CFCs, we develop a systematic and quantitative method to evaluate the protection achieved by CFCs using the metric of vulnerability. Our quantitative analysis indicates that existing CFC techniques are not only ineffective in providing protection from soft faults, but incur additional performance and power overheads. Our results show that software-only CFC protection schemes increase system vulnerability by 18%-21% with 17%-38% performance overhead and hybrid CFC protection increases vulnerability by 5%. Although the vulnerability remains almost the same for hardware-only CFC protection, they incur overheads of design cost, area, and power due to the hardware modifications required for their implementations. CCS Concepts: • Computer systems organization → Reliability; • Software and its engineering → Data flow architectures; Control structures;

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Section: Introductionmentioning

confidence: 99%

Control Flow Checking or Not? (for Soft Errors)

Rhisheekesan

Jeyapaul

Shrivastava

2019

ACM Trans. Embed. Comput. Syst.

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“…At the current technology node, a soft error may occur in a high-end server once every 170 hours, but it is expected to increase exponentially with technology scaling and reach alarming levels of once-per-day! [4] Chip Multiprocessors or CMPs are inherently good for reliability due to the availability of many cores, on which redundant computations can be performed for error detection, and/or correction. Many redundancy based techniques, at various levels of design space abstraction, based on Dual Modular Redundancy (DMR) [5], Triple Modular Redundancy (TMR) [6], and checkpointing [7] have been proposed to enable error detection and correction in CMPs.…”

Section: Introductionmentioning

confidence: 99%

UnSync: A Soft Error Resilient Redundant Multicore Architecture

Jeyapaul

Hong

Rhisheekesan

et al. 2011

2011 International Conference on Parallel Processing

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Abstract-Reducing device dimensions, increasing transistor densities, and smaller timing windows, expose the vulnerability of processors to soft errors induced by charge carrying particles. Since these factors are only consequences of the inevitable advancement in processor technology, the industry has been forced to improve reliability on general purpose Chip Multiprocessors (CMPs). With the availability of increased hardware resources, redundancy based techniques are the most promising methods to eradicate soft error failures in CMP systems. In this work, we propose a novel redundant CMP architecture (UnSync) that utilizes hardware based detection mechanisms (most of which are readily available in the processor), to reduce overheads during error free executions. In the presence of errors (which are infrequent), the always forward execution enabled recovery mechanism provides for resilience in the system. We design a detailed RTL model of our UnSync architecture and perform hardware synthesis to compare the hardware (power/area) overheads incurred. We compare the same with those of the Reunion technique, a state-of-the-art redundant multi-core architecture. We also perform cycle-accurate simulations over a wide range of SPEC2000, and MiBench benchmarks to evaluate the performance efficiency achieved over that of the Reunion architecture. Experimental results show that, our UnSync architecture reduces power consumption by 34.5% and improves performance by up to 20% with 13.3% less area overhead, when compared to Reunion architecture for the same level of reliability achieved.

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“…Soft errors are especially important for embedded systems which may be used inside humans, close to humans, in financial, medical, and security transactions, and even in hostile and enemy territory, where there is a critical need for dependable information. Although the soft error rate in embedded devices such as handhelds is about once-per-year today, due to its exponential growth rate with technology generations, it is expected to reach alarming levels of once-per-day in about a decade [13].…”

Section: Introductionmentioning

confidence: 99%

Cache vulnerability equations for protecting data in embedded processor caches from soft errors

2010

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Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, caches are most vulnerable to soft errors, and techniques at various levels of design abstraction, e.g., fabrication, gate design, circuit design, and microarchitecture-level, have been developed to protect data in caches. However, no work has been done to investigate the effect of code transformations on the vulnerability of data in caches. Data is vulnerable to soft errors in the cache only if it will be read by the processor, and not if it will be overwritten. Since code transformations can change the read-write pattern of program variables, they significantly effect the soft error vulnerability of program variables in the cache. We observe that often opportunity exists to significantly reduce the soft error vulnerability of cache data by trading-off a little performance. However, even if one wanted to exploit this trade-off, it is difficult, since there are no efficient techniques to estimate vulnerability of data in caches. To this end, this paper develops efficient static analysis method to estimate program vulnerability in caches, which enables the compiler to exploit the performance-vulnerability trade-offs in applications. Finally, as compared to simulation based estimation, static analysis techniques provide the insights into vulnerability calculations that provide some simple schemes to reduce program vulnerability.

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Reliability consideration for advanced microelectronics

Cited by 6 publications

References 0 publications

Control Flow Checking or Not? (for Soft Errors)

Control Flow Checking or Not? (for Soft Errors)

UnSync: A Soft Error Resilient Redundant Multicore Architecture

Cache vulnerability equations for protecting data in embedded processor caches from soft errors

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