Cache vulnerability equations for protecting data in embedded processor caches from soft errors

Abstract

Continuous technology scaling has brought us to a point, where transistors have become extremely susceptible to cosmic radiation strikes, or soft errors. Inside the processor, caches are most vulnerable to soft errors, and techniques at various levels of design abstraction, e.g., fabrication, gate design, circuit design, and microarchitecture-level, have been developed to protect data in caches. However, no work has been done to investigate the effect of code transformations on the vulnerability of data in caches. Data is vulnerable to soft errors in the cache only if it will be read by the processor, and not if it will be overwritten. Since code transformations can change the read-write pattern of program variables, they significantly effect the soft error vulnerability of program variables in the cache. We observe that often opportunity exists to significantly reduce the soft error vulnerability of cache data by trading-off a little performance. However, even if one wanted to exploit this trade-off, it is difficult, since there are no efficient techniques to estimate vulnerability of data in caches. To this end, this paper develops efficient static analysis method to estimate program vulnerability in caches, which enables the compiler to exploit the performance-vulnerability trade-offs in applications. Finally, as compared to simulation based estimation, static analysis techniques provide the insights into vulnerability calculations that provide some simple schemes to reduce program vulnerability.

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

“…Similarly, code transformations such as loop interchange and loop fusion, data layout transformations such as array placement and interleaving change the read/write pattern of variables in the cache. Some researchers study these interactions in detail [38,61,79,89] and show that by carefully selecting the compiler optimizations, a fine balance between performance and reliability can be obtained.…”

UnSync: A Soft Error Resilient Redundant Multicore Architecture

“…Solutions to increase the reliability of a system, in the presence of soft errors, hae been sought after at all levels of computer design abstraction e.g., chip packaging [9], device fabrication [10], circuit design [11], computer microarchitecture [12], compiler optimizations [13] and software design [14]. Though the techniques had been developed for single-processor systems, they could be made applicable to many-core systems; however the performance or hardware overhead in each would be multiplied by the number of cores it is applied to.…”

Modelling and mitigation of soft-errors in CMOS processors

“…Different methods to enhance the soft-error resilience of multi-core systems with regard to soft-errors have been already proposed at all levels of design hierarchy, including packaging level [Bau95], fabrication level [Can04], circuit design [Roc92] as well as software level [Shr10].…”