Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings

Tan, Xiaotian; Shi, C.-J.R.; Lungeanu, D.; Lee, Jyh-Chwen; Yuan, Li-Pen

doi:10.1145/309847.309880

Cited by 71 publications

(53 citation statements)

References 11 publications

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“…This assumption is not true anymore in many cases. Power grid networks which supply elements of large circuits with energy are of this special form [23,26]. Often these power grids are realized as an extra layer of elements in between the layers of transistors.…”

Section: Introductionmentioning

confidence: 99%

On Stability, Passivity and Reciprocity Preservation of ESVDMOR

Benner

Schneider

2011

Lecture Notes in Electrical Engineering

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The reduction of parasitic linear subcircuits is one of many issues in model order reduction (MOR) for VLSI design. This issue is well explored, but recently the incorporation of subcircuits from different modelling sources into the circuit model has led to new structural aspects: so far, the number of elements in the subcircuits was significantly larger than the number of connections to the whole circuit, the so called pins or terminals. This assumption is no longer valid in all cases such that the simulation of these circuits or rather the reduction of the model requires new methods. In [6,15,17], the extended singular value decomposition based model order reduction (ESVDMOR) algorithm is introduced as a way to handle this kind of circuits with a massive number of terminals. Unfortunately, the ESVDMOR approach has some drawbacks because it uses the SVD for matrix factorizations. In [5,22] the truncated SVD (TSVD) as an alternative to the SVD within the ESVDMOR is introduced. In this paper we show that ESVDMOR as well as the modified approach is stability, passivity, and reciprocity preserving under reasonable assumptions.

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Section: Introductionmentioning

confidence: 99%

On Stability, Passivity and Reciprocity Preservation of ESVDMOR

Benner

Schneider

2011

Lecture Notes in Electrical Engineering

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“…Peak noise usually occurs when the instantaneous switching current load becomes maximum [2] for a short duration with its energy spectrum lying in the high-frequency range [1]. Abundant research has been done to minimize peak noise for PDN design (e.g., [3][4][5][6]). …”

Section: Introductionmentioning

confidence: 99%

Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction.

Shi

Xiong

Chen

et al. 2009

2009 Asia and South Pacific Design Automation Conference

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“…Typically, the choices available to a supply net designer are to (i) appropriately size the supply net wires [1][2][3][4], (ii) perform topology optimization, i.e., to assign suitable pitches to the power grid wires and/or determine the optimal assignment of the pins to the pads and placement of pads on the power grid [5][6][7][8][9], and (iii) add decoupling capacitors [10], [11].…”

Section: Introductionmentioning

confidence: 99%

Partition-based algorithm for power grid design using locality

Singh

Sapatnekar

2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper presents an efficient heuristic algorithm, which employs a successive partitioning and grid refinement scheme, for designing the power distribution network of a chip. In our iterative procedure, the chip area is recursively bipartitioned, and the wire pitches and the wire widths of the power grid in the partitions are repeatedly adjusted to meet the voltage drop and current density specifications. By using the macromodels of the power grid constructed in the previous levels of partitioning, the scheme ensures that a small global power grid system is simulated in each iteration. The idea is based on the notion that due to the locality properties of the power grid, the effects of distant nodes and sources can be modeled more coarsely than nearby elements, and includes practical methods that enhance the convergence of the iterative conjugate-gradient based solution engine that is used in each step. Finally, a post-processing step at the end of the optimization is employed to maximize the alignment of wires in adjacent partitions. The effectiveness of the scheme is demonstrated by designing various power grids with real circuit parameters and realistic input current values. The proposed algorithm is able to design power grids comprising thousands of wires and more than a million electrical nodes in about 6 to 13 minutes. When compared to a multigrid-based power grid design scheme, it is found to save about 7% to 12% of wire area, and on an average is 14% faster.

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Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings

Cited by 71 publications

References 11 publications

On Stability, Passivity and Reciprocity Preservation of ESVDMOR

On Stability, Passivity and Reciprocity Preservation of ESVDMOR

Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction.

Partition-based algorithm for power grid design using locality

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