Reliability evaluation on sense-switch p-channel flash

Abstract

In this paper, the reliability of sense-switch p-channel flash is evaluated extensively. The endurance result indicates that the p-channel flash could be programmed and erased for more than 10 000 cycles; the room temperature read stress shows negligible influence on the p-channel flash cell; high temperature data retention at 150 °C is extrapolated to be about 5 years and 53 years corresponding to 30% and 40% degradation in the drive current, respectively. Moreover, the electrical parameters of the p-channel flash at different operation temperature are found to be less affected. All the results above indicate that the sense-switch p-channel flash is suitable to be used as the configuration cell in flash-based FPGA.

Memory Window Ratio Enhancement of p-Type WSe2 Memtransistors Using Dielectric GeSe2 Nanosheets with Asymmetric Interfaces for Neuromorphic Computing

“…Neuromorphic computing, a disruptive computation technology, aims to address these bottlenecks by mimicking parallel information processing and storage in a human brain. , Two solid nonvolatile memory (NVM) architectures, two-terminal memristors − and three-terminal memtransistors, , have been proposed for implementing neuromorphic computing. As the terminals for reading and writing are decoupled, basic memory operations in the memtransistors become nondestructive, which can considerably simplify addressability in crossbar arrays and efficiently enable tunable learning rules and biorealistic functions, e.g., heterosynaptic plasticity, continuous learning, neuromodulation, and multitemporal plasticity. , The most common memtransistor is based on the floating gate (FG) type structure, where charges are stored in the floating gate to modify channel conductivity. − However, gate dielectrics serving as a Fowler–Nordheim (FN) tunnel barrier in the FG structure for hot-electron injection lead to high power consumption, slow programming speed, and poor device endurance. , In contrast, a direct charge-trapping memtransistor (DCTM) is built based on a simple metal–insulator–semiconductor field-effect transistor architecture with a tailor-made band alignment, which demonstrates a promising potential for next-generation memories. − …”

“…10−12 However, gate dielectrics serving as a Fowler−Nordheim (FN) tunnel barrier in the FG structure for hot-electron injection lead to high power consumption, slow programming speed, and poor device endurance. 13,14 In contrast, a direct charge-trapping memtransistor (DCTM) is built based on a simple metal− insulator−semiconductor field-effect transistor architecture with a tailor-made band alignment, which demonstrates a promising potential for next-generation memories. 15−17 Despite the novel structure and outstanding properties of DCTMs, their development is still in an incipient stage, far behind that of their FG counterparts.…”

Research on eigenstate current control technology of Flash-based FPGA

“…There is about μA conduction current between the source and drain of each Flash cell. In the wiring switch matrix [3] , the two signals with opposite polarity will serve as the input of the signal selector MUX, thus form-ing a conducting current between the two Flash cells. Flashbased FPGA has several or even tens of millions of Flash cells.…”