2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS) 2011
DOI: 10.1109/mwscas.2011.6026672
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Reliability improvement in multicore architectures through computing in embedded memory

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Cited by 6 publications
(2 citation statements)
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“…In this paper, we optimize the same for coarse-grained regular data path, common to algorithmic tasks. The only work on MBC in a multicore architecture is done by Hajimiri et al [5]. They proposed an architecture for improving reliability in multicore architectures using MBC.…”
Section: Introductionmentioning
confidence: 99%
“…In this paper, we optimize the same for coarse-grained regular data path, common to algorithmic tasks. The only work on MBC in a multicore architecture is done by Hajimiri et al [5]. They proposed an architecture for improving reliability in multicore architectures using MBC.…”
Section: Introductionmentioning
confidence: 99%
“…Соответственно, реконфигурация производится простой перезаписью этих значений, а вычисления -обращениями к ним. Это решение с детальным обоснованием выбора описаны в [3][4][5]. Крупногранулярных решений множество.…”
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