Reliability of InGaAs/InP HBTs with InP passivation structure

Yamabi, Ryuji; Kotani, Kenji; Kawasaki, Takeshi; Yanagisawa, Masaki; Yaegassi, Seiji; Yano, Hiroshi

doi:10.1109/iciprm.2003.1205328

Cited by 9 publications

(2 citation statements)

References 4 publications

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“…We have employed the etching mask with projections on four corners for the emitter contact mesa etching in order to preclude excessive etching in <010> directions of the emitter contact layer. Consequently, high uniformity, high reproducibility and high reliability have been achieved [6].…”

Section: Introductionmentioning

confidence: 99%

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Highly-reliable and reproducible InGaAs/InP double heterojunction bipolar transistor utilizing all-wet etching process for triple mesa formation

Yanagisawa¹,

Watanabe²,

Kawasaki³

et al. 2013

2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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The authors have succeeded in making a robust fabrication process applied to InP-based double heterojunction bipolar transistors. The process, featuring all-wet etching method for formation of triple-mesa structure, has shown markedly high reproducibility and reliability. The variation of the current gain has been 4.6% through 130 wafers, and the mean time to failure at the junction temperature of 100ºC has been longer than 4 x 10 6 hours, whose criterion is a 5% change in current gain. These excellent results show that our structure of DHBT, which has an InP passivation layer on the surface of the base layer, and our all-wet mesa formation process, are sufficient to be applied to the manufacturing of integrated circuits.

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Section: Introductionmentioning

confidence: 99%

“…The authors conclude that the markedly high reliability is an advantage of the thin InP passivation layer on the base layer, which effectively suppresses the increase of leakage current between the emitter and the base electrodes [6] [7].…”

mentioning

confidence: 97%

Highly-reliable and reproducible InGaAs/InP double heterojunction bipolar transistor utilizing all-wet etching process for triple mesa formation

Yanagisawa¹,

Watanabe²,

Kawasaki³

et al. 2013

2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

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show abstract

High etch rate and low temperature InP backside via etching using HI-based inductively coupled plasma

Kotani¹,

Kawasaki²,

Miyazaki³

et al.

16th IPRM. 2004 International Conference on Indium Phosphide and Related Materials, 2004.

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We have successfully demonstrated a high etch rate and low temperature backside via etching into 1nP using HI-based ICP. An average InP etch rate of 2.0 p d m i n at a wafer temperature of 130 "C was obtained. Using this etching, 80 pm diameter backside vias were formed into 100 pm thick InP with a simple process. The vias show good profile and smooth surface over a 3-inch diameter wafer. From s-parameter measurements, the average via inductance of 12.1 pH was extracted and the inductance coincides with a calculated value. To evaluate reliability, a heat cycle test under a condition of temperature cycling from 150 "C to -65 "C was carried out. After testing of 100 cycles, all vias satisfied the test requirements. These results show that our InP backside via process is promising for practical applications.

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Highly reliable InP-based HBTs with a ledge structure operating at current density over 2 mA/μm/sup 2/

Fukai

Kurishima

Ida³

et al.

International Conference on Indium Phosphide and Related Materials, 2005.

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Reliability of InGaAs/InP HBTs with InP passivation structure

Cited by 9 publications

References 4 publications

Highly-reliable and reproducible InGaAs/InP double heterojunction bipolar transistor utilizing all-wet etching process for triple mesa formation

Highly-reliable and reproducible InGaAs/InP double heterojunction bipolar transistor utilizing all-wet etching process for triple mesa formation

High etch rate and low temperature InP backside via etching using HI-based inductively coupled plasma

Highly reliable InP-based HBTs with a ledge structure operating at current density over 2 mA/μm/sup 2/

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Reliability of InGaAs/InP HBTs with InP passivation structure

Cited by 9 publications

References 4 publications

Highly-reliable and reproducible InGaAs/InP double heterojunction bipolar transistor utilizing all-wet etching process for triple mesa formation

Highly-reliable and reproducible InGaAs/InP double heterojunction bipolar transistor utilizing all-wet etching process for triple mesa formation

High etch rate and low temperature InP backside via etching using HI-based inductively coupled plasma

Highly reliable InP-based HBTs with a ledge structure operating at current density over 2 mA/&#x03BC;m/sup 2/

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Highly reliable InP-based HBTs with a ledge structure operating at current density over 2 mA/μm/sup 2/