Reliability of scrubbing recovery-techniques for memory systems

Saleh, Abdol; Serrano, Juan José; Patel, J.H.

doi:10.1109/24.52622

Cited by 174 publications

(92 citation statements)

References 6 publications

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“…To minimize the performance overhead, the cache miss to refetch the cacheline can be scheduled during cache idle cycles. Notice that our scrubbing scheme is different from the schemes in [40], [31], [41] that scrub the data by recomputing the ECC TABLE 3 Overhead of the Combined Scheme Fig. 11 The temporal vulnerability factor of the data array in the instruction cache at different granularities of a cacheline or 32-bit data.…”

Section: Csmentioning

confidence: 99%

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

Wang

Ziavras

2009

IEEE Trans. Comput.

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Abstract-Soft errors induced by energetic particle strikes in on-chip cache memories have become an increasing challenge in designing new generation reliable microprocessors. Previous efforts have exploited information redundancy via parity/ECC codings or cacheline duplication for information integrity in on-chip cache memories. Due to various performance, area/size, and energy constraints in various target systems, many existing unoptimized protection schemes may eventually prove significantly inadequate and ineffective. In this paper, we propose a new framework for conducting comprehensive studies and characterization on the reliability behavior of cache memories, in order to provide insight into cache vulnerability to soft errors as well as design guidance to architects for highly efficient reliable on-chip cache memory design. Our work is based on the development of new lifetime models for data and tag arrays residing in both the data and instruction caches. Those models facilitate the characterization of cache vulnerability of stored items at various lifetime phases. We then exemplify this design methodology by proposing reliability schemes targeting at specific vulnerable phases. Benchmarking is carried out to showcase the effectiveness of our approach.

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Section: Csmentioning

confidence: 99%

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

Wang

Ziavras

2009

IEEE Trans. Comput.

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“…As an additional protection, the error-free data output can be fed back to the source memory word and can be re-written, in order to ensure the integrity of the memory data. When the error-free data is rewritten periodically, this process is called scrubbing, and it can either be done via software or hardware controller [10].…”

Section: Introductionmentioning

confidence: 99%

Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair

Mayuga

Yamato

Yoneda

et al. 2016

IEICE Trans. Inf. & Syst.

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SUMMARY Embedded memory is extensively being used in SoCs, and is rapidly growing in size and density. It contributes to SoCs to have greater features, but at the expense of taking up the most area. Due to continuous scaling of nanoscale device technology, large area size memory introduces aging-induced faults and soft errors, which affects reliability. In-field test and repair, as well as ECC, can be used to maintain reliability, and recently, these methods are used together to form a combined approach, wherein uncorrectable words are repaired, while correctable words are left to the ECC. In this paper, we propose a novel in-field repair strategy that repairs uncorrectable words, and possibly correctable words, for an ECC-based memory architecture. It executes an adaptive reconfiguration method that ensures 'fresh' memory words are always used until spare words run out. Experimental results demonstrate that our strategy enhances reliability, and the area overhead contribution is small. key words: memory repair, memory reliability, in-field test and repair, ECC, in-field repair strategy, remapping

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“…Selective checking is presented in Section 3.3 as a simpler alternative to the first two when a cache has multi-way set associativity. In Section 3.4, we also discuss integration of cache scrubbing [11] into the proposed architectures to enhance their capabilities.…”

Section: New Architectural Approachesmentioning

confidence: 99%

“…To further enhance the data integrity, we can scrub off the latent errors in the D-cache whenever possible. Soft error scrubbing is accomplished by reading out the data and check bits, verifying their correctness, and writing back the corrected data [11]. Scrubbing is more advantageous to caches protected by a low capability check code.…”

Section: Cache Scrubbingmentioning

confidence: 99%