Reliability of single and dual Layer Pt nanocrystal devices for NAND flash applications: A 2-region model for endurance defect generation

Performance and Reliability Study of Single-Layer and Dual-Layer Platinum Nanocrystal Flash Memory Devices Under NAND Operation

“…Although the use of DL NC structure has been reported in literature to improve the memory window and retention over a SL NC structure [22], [25], [26], extensive reliability assessment of the DL structure is still lacking. Preliminary investigations have demonstrated DL structure to have significantly better P/E cycling endurance reliability compared to SL structure, with > 10 4 P/E cycle endurance at 7-V memory window for the optimized device, as shown in the author's previous works [27]- [29].…”

“…DL devices with a thick ILF are observed to have better endurance reliability over devices with thin ILF. Improvement in the DL endurance over SL devices is also noted and explained by the two-region model [28], P/E cycling endurance of the SL devices is unsatisfactory, while that for the DL devices, it is shown to be satisfactory to meet the minimum MLC flash requirements [24]. Finally, a thorough investigation of the postcycling retention reliability data is presented to complete the understanding of P/E stress-induced device degradation in NC devices.…”

“…However, both P-and E-V FB levels are observed to shift toward more negative V FB , suggesting the permanent positive charge trapping in the gate stack for both SL and DL devices. Hole injection and subsequent trapping in the gate stack during erase operation is suggested as the primary reason for the negative shift in V FB and the eventual breakdown in the NC gate stacks [28]. Larger area coverage in DL compared to SL limits the hole injection during erase, thus improving the endurance reliability [28].…”

Performance and Reliability of Au and Pt Single-Layer Metal Nanocrystal Flash Memory Under nand (FN/FN) Operation

“…The E-state V FB of Pt devices shifts by nearly −0.2 V before breakdown, indicating permanent positive charge trapping in the gate dielectric. The permanent positive charge trapping in the gate stack of Pt NC devices is possibly due to the hole injection from the substrate during erase [24].…”

“…In one of our recent work [24], it has been shown that the degradation in the Pt NC gate stack is caused primarily by hole injection during erase and the negative shift of P/E levels is due to the permanent hole trapping in the CD. A sudden loss of programmability is due to formation of leakage path between the channel and CG, which prevents further P/E operation on the NC.…”