Reliability on ARM Processors Against Soft Errors Through SIHFT Techniques

Abstract

ARM processors are leaders in embedded systems, delivering high-performance computing, power efficiency, and reduced cost. For this reason, there is a relevant interest for its use in the aerospace industry. However, the use of sub-micron technologies has increased the sensitivity to radiation-induced transient faults. Thus, the mitigation of soft errors has become a major concern. Software-Implemented Hardware Fault Tolerance (SIHFT) techniques are a low-cost way to protect processors against soft errors. On the other hand, they cause high overheads in the execution time and memory, which consequently increase the energy consumption. In this work, we implement a set of software techniques based on different redundancy and checking rules. Furthermore, a low-overhead technique to protect the program execution flow is included. Tests are performed using the ARM Cortex-A9 processor. Simulated fault injection campaigns and radiation test with heavy ions have been performed. Results evaluate the trade-offs among fault detection, execution time, and memory footprint. They show significant improvements of the overheads when compared to previously reported techniques.

Radiation hardening efficiency of gate sizing and transistor stacking based on standard cells

“…This is not an exhaustive list of effects known as Singe-Event Effects (SEE) [7]. Radiation Hardening by Design (RHBD) techniques have been developed to cope with radiation effects on electronic circuits at different levels of abstraction ranging from circuit layout to system and software design [8][9][10][11][12][13]. These techniques can provide mitigations from fault masking to detection and recovery of the system.…”

Sofia: An Automated Framework for Early Soft Error Assessment, Identification, and Mitigation

“…The application hardening module integrates data-flow mitigation techniques because most soft errors affect data-flow rather than the system's control-flow [38]. The underlying software-based mitigation techniques are architecture-independent, and their development is underpinned by a set of rules proposed in [39], which target data-flow strategies that aim to detect faults affecting values stored in register banks and memory elements.…”

Data Analysis and Results of the Radiation-Tolerant Collaborative Computer On-Board OPTOS CubeSat

“…A well-known disadvantage of software hardening is the overhead that it is being added both in terms of execution time and in terms of memory usage. However, some new methodologies, as presented in [14], have shown to improve execution time overhead while, at the same time, increasing the reliability of the system against Single Event Functional Interrupt (SEFI) errors. Nevertheless, software techniques are only a partial solution, since Single Event Latch-up (SEL) and Total Ionizing Dose (TID) effects on microelectronics may only be dealt by hardware approaches.…”