Reliable and self-repairing sram in nano-scale technologies using leakage and delay monitoring

Mukhopadhyay, Saibal; Kang, Kunhyuk; Mahmoodi, Hamid; Roy, Kaushik

doi:10.1109/test.2005.1584080

Cited by 34 publications

(41 citation statements)

References 12 publications

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“…For memory dominated structures, the SRAM array lookups have significantly more regularity and allow for dynamic partitioning and resizing which may allow them to improve performance in an energy-efficient manner by sacrificing capacity [30]. There has been a significant amount of work in adapting SRAM structures for use in both lowvoltage modes and severe parameter variation [25,30,31]. In contrast, logic dominated structures in the processor backend, most notably execution units, would be difficult to accelerate without significant impact to the power budget.…”

Section: Background and Motivationmentioning

confidence: 99%

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Identifying and predicting timing-critical instructions to boost timing speculation

Xin¹,

Joseph²

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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Circuit-level timing speculation has been proposed as a technique to reduce dependence on design margins and eliminating power/performance overheads. Recent work has proposed microarchitectural methods to dynamically detect and recover from timing errors in processor logic. To a large extent existing work has relied on statistical error models and has not evaluated potential disparity of error rates at the level of static instructions. In this paper, we analyze gatelevel hardware models for an execution pipeline and demonstrate pronounced locality in instruction-level error rates due to value locality and data dependences. We propose timing error prediction to dynamically anticipate timing errors at the instruction-level and error padding techniques to avoid the full recovery cost of timing errors. We show that with simple prediction strategies our mechanism can reduce 80% of the performance penalty incurred by error recovery on average. This allows us to alleviate some limitations of timing speculation and improves energy-efficiency by 21% when compared to baseline timing speculation techniques using the same dynamic adaptive tuning mechanism.

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Section: Background and Motivationmentioning

confidence: 99%

“…Due to overheads we do not use Razor to recover from timing errors in large SRAM structures. We instead implement resizing methods to trade off the capacity for energy savings for I-Cache and DCache [30]. We apply simple block-level resizing where blocks are selectively mapped out in the I-Cache and D-Cache.…”

Section: Dynamic Voltage Tuning and Optimizationmentioning

confidence: 99%

Identifying and predicting timing-critical instructions to boost timing speculation

Xin¹,

Joseph²

2011

Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

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“…Atspeed logic and memory built-in self test (BIST) techniques can be employed as well for faster and any time computation of the signatures. Approximations using on-chip monitors (e.g., ring oscillators or monitors such as [22]) can work as well. Since signature measurement involves using test techniques with well understood overheads, in this work we do not discuss these methods in more detail.…”

Section: Signature Choice and Measurementmentioning

confidence: 99%

Software adaptation in quality sensitive applications to deal with hardware variability

Pant

Gupta

Schaar

2010

Proceedings of the 20th Symposium on Great Lakes Symposium on VLSI

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In this work, we propose a method to reduce the impact of process variations by adapting the application's algorithm at the software layer. We introduce the concept of hardware signatures as the measured post manufacturing hardware characteristics that can be used to drive software adaptation across different die. Using H.264 encoding as an example, we demonstrate significant yield improvements (as much as 40% points at 0% over-design), a reduction in overdesign (by as much as 10% points at 80% yield) as well as application quality improvements (about 2.6dB increase in average PSNR at 80% yield). Further, we investigate implications of limited information exchange (i.e. signature measurement granularity) on yield and quality. We show that our proposed technique for determining optimal signature measurement points results in an improvement in PSNR of about 1.3dB over naive sampling for the H.264 encoder. We conclude that hardware-signature based application adaptation is an easy and inexpensive (to implement), better informed (by actual application requirements) and effective way to manage yield-cost-quality tradeoffs in applicationimplementation design flows.

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“…Reducing subthreshold leakage current causes variation in V th resulting in various functional failures in SRAM. These failures can be avoided by adaptively biasing the body since threshold voltage (V th ) is a function of body bias (Mukopadhyay et al, 2005;Lu and Naing, 2005). However this scheme requires larger bit cell area and overall SRAM area.…”

Section: Introductionmentioning

confidence: 99%

Design For Test Technique for Leakage Power Reduction in Nanoscale Static Random Access Memory

Sivamangai¹,

Gunavathi²

2011

Journal of Computer Science

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Problem statement: As technology scales down, the integration density of transistors increases and most of the power is dissipated as leakage. Leakage power reduction is achieved in Static Random Access Memory (SRAM) cells by increasing the source voltage (source biasing) of the SRAM array. Another promising issue in nanoscaled devices is the process parameter variations. Due to these variations, higher source voltage causes the data stored in the cells of the SRAM array to flip (weak cell) in the standby mode resulting in hold failure. The weak cells identified are replaced using redundant columns. Maximum source voltage that can be applied to reduce the leakage power without any failure depends on the number of redundant columns available to repair the weak cells. Approach: This study proposes a novel Design For Test (DFT) technique to reduce the number of March tests, thus reducing the test time using a source bias (V SB ) predictor. In the proposed method, V SB predictor predicts the initial source bias voltage to be applied to the SRAM array. The proposed DFT verified by designing an 8×16 SRAM array in 90 nm technology. March algorithm was used to identify the weak cells and predict the maximum source voltage from '0' mV. This process was run large number of March tests consuming more test time. Results and discussion: The predicted V SB helps to make a fast convergence of maximum V SB to be applied, which will improve the speed performance of the adaptive source bias and saves the test time by 60 %.

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Reliable and self-repairing sram in nano-scale technologies using leakage and delay monitoring

Abstract: The

Cited by 34 publications

References 12 publications

Identifying and predicting timing-critical instructions to boost timing speculation

Identifying and predicting timing-critical instructions to boost timing speculation

Software adaptation in quality sensitive applications to deal with hardware variability

Design For Test Technique for Leakage Power Reduction in Nanoscale Static Random Access Memory

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