Reliable multicore processors for NASA space missions

Villalpando, Carlos Y.; Rennels, D. A.; Some, Raphael; Cabanas-Holmen, Manuel

doi:10.1109/aero.2011.5747447

Cited by 30 publications

(10 citation statements)

References 2 publications

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“…Maestro, a 49-core rad-hard processor from the OPERA program [18], is the first manycore processor to target space applications. Figure 1 overviews the Maestro architecture.…”

Section: Rad750 Maestromentioning

confidence: 99%

Unifying manycore and FPGA processing with the RUSH architecture

Beresini

Ricketts

Taylor

2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Because of the constraints of space computing, the set of available processing technologies is limited. Conventionally, designers have had to choose from programmable radhard processors and fixed ASIC solutions. FPGAs provide significantly better power-performance efficiency than general purpose processors, but are more costly to program and are less flexible. For terrestrial applications, manycore processors have been adopted for a class of applications where both performance and flexible programmability are important metrics. Maestro, the first rad-hard manycore processor, has the potential to enable new capabilities for space computation. However, for many applications, certain timing-critical tasks still require the performance efficiency of an FPGA co-processor. Moreover, integrating such heterogeneous systems is challenging because the individual processing substrates have differing internal programming models. As a result, data sharing and dynamic workload scheduling across heterogeneous architectures are often suboptimal and hindered by poor scalability. The Rad-hard Unified Scalable Heterogeneous (RUSH) architecture is a heterogeneous processing platform with both a manycore chip and an FPGA. RUSH provides a unified programming model across both chips to allow for rapid development of scalable and efficient implementations. This paper overviews RUSH's technical approach and presents an example application: a WiMAX radio transceiver.

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“…Maestro, a 49-core rad-hard processor from the OPERA program [18], is the first manycore processor to target space applications. Figure 1 overviews the Maestro architecture.…”

Section: Rad750 Maestromentioning

confidence: 99%

Unifying manycore and FPGA processing with the RUSH architecture

Beresini

Ricketts

Taylor

2011

2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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“…Moreover, these devices provide a great flexibility because they allow implementing different multi-processing modes and programming paradigms. Hence, avionics and spacecraft industries are interested in validating the use of multi-core and many-core devices for their applications [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Evaluating the SEE Sensitivity of a 45 nm SOI Multi-Core Processor Due to 14 MeV Neutrons

Ramos

Vargas

Baylac

et al. 2016

IEEE Trans. Nucl. Sci.

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Abstract-The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processsing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processsing mode used.

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“…Recent trend in on-board computing systems is the use of multicore processors for enhancing the reliability [11]. Multicore processors are inherently redundant in terms of processor cores, I/O, power supply pins and memory ports that can be used for software or hardware fault-tolerant computing.…”

Section: Multicore Fault-tolerant Computingmentioning

confidence: 99%

“…or a set of tightly-coupled computers if the available computing resources are effectively utilized [6] [6,11]. This requires that redundancy is eliminated, wherever possible, however removing redundant nodes can expose processors and networks to faults, leading to degradation of system efficiency and incorrect results.…”

mentioning

confidence: 99%

Survey and future directions of fault-tolerant distributed computing on board spacecraft

Fayyaz

Vladimirova

2016

Advances in Space Research

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Current and future space missions demand highly reliable on-board computing systems, which are capable to carry out high-performance data processing. At present no single computing scheme could efficiently tackle high-performance computing as well as reliability. This paper aims to address that gap. In the first part of the paper, a detailed survey of fault-tolerant distributed computing systems for space applications is presented. Fault types and performance parameters for assessment of a fault-tolerant system are introduced. Redundancy schemes for distributed systems are analysed. A review of the state-of-the-art on fault-tolerant distributed systems is presented and limitations of current approaches are discussed. In the second part of the paper, a new fault-tolerant distributed computing platform with wireless links among the computing nodes is proposed. Novel algorithms, enabling important aspects of the architecture, such as time slot priority adaptive fault-tolerant channel access and fault-tolerant distributed computing using task migration are introduced.

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Reliable multicore processors for NASA space missions

Cited by 30 publications

References 2 publications

Unifying manycore and FPGA processing with the RUSH architecture

Unifying manycore and FPGA processing with the RUSH architecture

Evaluating the SEE Sensitivity of a 45 nm SOI Multi-Core Processor Due to 14 MeV Neutrons

Survey and future directions of fault-tolerant distributed computing on board spacecraft

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