Reliable SoC Design and Implementation of SHA-3-HMAC Algorithm with Attack Protection

Zhou, Tao; Zhu, Yongxin; Jing, Naifeng; Nan, Tianhao; Li, Wanyi; Peng, Bo

doi:10.1109/smartcloud49737.2020.00025

Cited by 7 publications

(6 citation statements)

References 18 publications

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“…Secure storage practices, including encryption and access control measures, are applied to voting data, ensuring protection against unauthorized access and tampering. The use of cryptographic hash functions creates a chain of custody for voting data, emphasizing established standards like SHA-256 for data security within the university's e-voting systems [23].…”

Section: Signature and Hashmentioning

confidence: 99%

Blockchain-based e-voting system in a university

Marouan,

Badrani,

Kannouf

et al. 2024

IJEECS

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The blockchain-based electronic voting (e-voting) system, offers universities a safe, easy-to-use platform that enhances accuracy and integrity. Despite that, it is challenging to integrate the blockchain-based e-voting system with current platforms and private data. Managing latency is another requirement during the blockchain transactions (votes/elections). In this work, we suggested a novel system that uses smart contracts on the consortium blockchain to address these constraints. The voters and electors in a university can vote and elect respecting the rules established in smart contracts. The miners validate transactions using proof of work (PoW) and proof of stake (PoS). Data integrity and voter validity are ensured via the SHA-256 hash algorithm and the ECDSA signature. The implementation results demonstrate that the suggested method works better than the state-of-the-art. exceeds the state-of-the-art in terms of gas cost and execution time.

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Section: Signature and Hashmentioning

confidence: 99%

Blockchain-based e-voting system in a university

Marouan,

Badrani,

Kannouf

et al. 2024

IJEECS

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“…Due to their nature, such attacks take the name Side-Channel Attacks (SCAs), and Figure 3 SCAs are widely documented in the literature and constitute one of the hottest topics in the cybersecurity field. An exhaustive and systematic review of SCAs can be found in [44][45][46], while [47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63] report several examples of the most diffused categories of attacks that exploit the physical implementation of a device, which are listed below:…”

Section: Rotmentioning

confidence: 99%

“…Power analysis [53][54][55][56][57][58][59][60][61]64,65]: This family of attacks is one of the most effective on both hardware and software implementations, and it exploits the power consumption of underlying physical circuits. Concerning the software case, if each opcode of the instruction set architecture can be associated with a different and specific power trace shape, then the series of operations performed by a routine is revealed; on the hardware side, data dependencies over different power traces can be analyzed to recover secret information.…”

mentioning

confidence: 99%

Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments

Crocetti,

Nannipieri,

Di Matteo

et al. 2023

Electronics

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Cyberattacks and cybercriminal activities constitute one of the biggest threats in the modern digital era, and the frequency, efficiency, and severity of attacks have grown over the years. Designers and producers of digital systems try to counteract such issues by exploiting increasingly robust and advanced security mechanisms to provide secure execution environments aimed at preventing cyberattacks or, in the worst case, at containing intrusions by isolation. One of the most significative examples comes from General Purpose Processor (GPP) manufacturers such as Intel, AMD, and ARM, which in the last years adopted the integration of dedicated resources to provide Trusted Execution Environments (TEEs) or secure zones. TEEs are built layer by layer on top of an implicitly trusted component, the Root-of-Trust (RoT). Since each security chain is only as strong as its weakest link, each element involved in the construction of a TEE starting from the RoT must be bulletproof as much as possible. In this work, we revise and propose a design methodology to implement in both hardware (HW) and software (SW) highly featured and robust security blocks by highlighting the key points that designers should take care of, and the key metrics that should be used to evaluate the security level of the developed modules. We also include an analysis of the state of the art concerning RoT-based TEEs, and we illustrate a case study that documents the implementation of a cryptographic coprocessor for the secure subsystem of the Rhea GPP from the European Processor Initiative (EPI) project, according to the presented methodology. This work can be used by HW/SW security module designers as a cutting-edge guideline.

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“…More importantly, the introduced errors result in an incorrect KECCAK state, rendering the integrity message output untrustworthy. So far, only a handful of fault detection algorithms have been developed to increase the KECCAK implementation's resilience [10][11][12][13][14][15][16][17][18][19]. Mestiri et al proposed in [10] an effective error detection technique based on modifying the KECCAK architecture.…”

Section: Introductionmentioning

confidence: 99%

“…More importantly, the introduced errors result in an incorrect KECCAK state, rendering the integrity message output untrustworthy. So far, only a handful of fault detection algorithms have been developed to increase the KECCAK implementation’s resilience [ 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 ].…”

Section: Introductionmentioning

confidence: 99%

High-Speed Hardware Architecture Based on Error Detection for KECCAK

Mestiri

Barraj

2023

Micromachines

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The hash function KECCAK integrity algorithm is implemented in cryptographic systems to provide high security for any circuit requiring integrity and protect the transmitted data. Fault attacks, which can extricate confidential data, are one of the most effective physical attacks against KECCAK hardware. Several KECCAK fault detection systems have been proposed to counteract fault attacks. The present research proposes a modified KECCAK architecture and scrambling algorithm to protect against fault injection attacks. Thus, the KECCAK round is modified so that it consists of two parts with input and pipeline registers. The scheme is independent of the KECCAK design. Iterative and pipeline designs are both protected by it. To test the resilience of the suggested detection system approach fault attacks, we conduct permanent as well as transient fault attacks, and we evaluate the fault detection capabilities (99.9999% for transient faults and 99.999905% for permanent faults). The KECCAK fault detection scheme is modeled using VHDL language and implemented on an FPGA hardware board. The experimental results show that our technique effectively secures the KECCAK design. It can be carried out with little difficulty. In addition, the experimental FPGA results demonstrate the proposed KECCAK detection scheme’s low area burden, high efficiency and working frequency.

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Reliable SoC Design and Implementation of SHA-3-HMAC Algorithm with Attack Protection

Cited by 7 publications

References 18 publications

Blockchain-based e-voting system in a university

Blockchain-based e-voting system in a university

Design Methodology and Metrics for Robust and Highly Qualified Security Modules in Trusted Environments

High-Speed Hardware Architecture Based on Error Detection for KECCAK

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