Relief of hot carrier constraint on submicron CMOS devices by use of a buried channel structure

Nakahara, M.; Hiruta, Y.; Noguchi, T.; Yoshida, M.; Maeguchi, K.; Kanzaki, K.

doi:10.1109/iedm.1985.190940

Cited by 10 publications

(4 citation statements)

References 4 publications

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“…Techniques proposed to accomplish this include either a buried channel device with a lightly doped drain [48] or a retrogade n-profile for the LDD region [49]. Other MOSFET device structures have been proposed, like the buried drain D-MOSFET [50], for which the reliability potential in VLSI has not yet been assessed.…”

Section: Jmos Device Structurementioning

confidence: 99%

A modified lightly doped drain structure for VLSI MOSFET's

Bampi

Plummer

1986

IEEE Trans. Electron Devices

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Section: Jmos Device Structurementioning

confidence: 99%

A modified lightly doped drain structure for VLSI MOSFET's

Bampi

Plummer

1986

IEEE Trans. Electron Devices

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“…The superiority in device characteristics of the p' poly gate MOSFET to the n' poly gate MOSFET has been reported [1,2]. By use of the p' poly gate PMOSFET which has a surface channel type, the short channel effect and subthreshold characteristics are improved.…”

Section: Introductionmentioning

confidence: 99%

+ BT Instability in P<sup>+</sup>poly gate MOS structure

Hiruta

Matsuoka²,

Hama³

et al. 1987

1987 International Electron Devices Meeting

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Long term reliability of p' poly gate MOS structure with thin gate oxide was investigated and compared with n' poly gate. Instability in positive low bias temperature (+BT) stress was found out in p' poly gate. Increase of interface states and negative flat band voltage shift were observed after +BT stress test.Increase of interface states does not depend on boron dose into the poly Si gate and phosphorus gettring process, and no interface state generatp appears in n+ poly gate containing implanted borons. So, the mobile ions and borons are not origin of the interface state generation.Therefore, the only one mechanism, which is not denied, is that holes are injected from p' poly gate into the oxide and generate interface states.

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“…The superiority in device characteristics for the p+ poly gate MOSFET, compared to the n+ poly gate MOSFET, has been reported [1]- [3]. By using a p+ poly gate PMOSFET with a surface channel, the shortchannel effects are significantly improved, compared with the n+ poly gate PMOSFET, which has a buried channel.…”

mentioning

confidence: 98%

“…The reliability of the gate electrode and the gate oxide is an important factor in integrating MOSFET's, and long-term reliability has been studied for n+ poly MOS structures [7]- [9]. Concerning p+ poly gate reliability, hot-carrier effects for MOS structures have been reported [3], [lo]- [12]. However, there have been very few reports about long-term reliability, specifically at moderate stress conditions, such as low electric field bias temperature stress (BT).…”

mentioning

confidence: 99%

Interface state generation under long-term positive-bias temperature stress for a p/sup +/ poly gate MOS structure

Hiruta

Matsuoka

Hama

et al. 1989

IEEE Trans. Electron Devices

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Abstraet-Long-term reliability for a p+ poly gate MOS structure was tested under low electric field bias temperature (BT) stress in comparison with an n+ poly gate. A significant increase in interface state density was observed for the pf poly gate MOS structure under positive bias conditions. This phenomenon was not observed in the n + poly gate case. The mechanism for this interface state increase was investigated in detail. Several possible causes, such as mobile ions, excess boron concentration in the gate oxide, electron injection from the substrate, impact ionization in the gate oxide, and bole injection from the gate electrode, were considered. All of the causes, except hole injection, were obviated by experiments. Although hole injection current was too small to be detected, hole injection from the p+ poly gate is a possible cause, which could explain the interface state generation under positive-bias temperature test. For applying a p+ poly gate to CMOS structures, care should be taken when positive bias is applied to the gate electrode.

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Relief of hot carrier constraint on submicron CMOS devices by use of a buried channel structure

Cited by 10 publications

References 4 publications

A modified lightly doped drain structure for VLSI MOSFET's

A modified lightly doped drain structure for VLSI MOSFET's

+ BT Instability in P<sup>+</sup>poly gate MOS structure

Interface state generation under long-term positive-bias temperature stress for a p/sup +/ poly gate MOS structure

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