REPAIR: A Reliable Partial-Redundancy-Based Router in NoC

Xie, Lihua; Mei, Kuizhi; Li, Yuhai

doi:10.1109/nas.2013.28

Cited by 15 publications

(7 citation statements)

References 8 publications

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“…Thus, on average 28.5 faults cause the failure of the NoCGuard router. We compare MDTF of our NoCGuard router with the existing reliable routers such as BulletProof [22], RoCo [23], Vicis [24], PVS [26], REPAIR [25], SHIELD [28], DRS [27] and HPR [29]. From Figure 10, it is evident that the MDTF of NoCGuard is greater than the existing reliable router architectures.…”

Section: Mdtf Estimation Of Nocguard Routermentioning

confidence: 99%

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NoCGuard: A Reliable Network-on-Chip Router Architecture

et al. 2020

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Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.Electronics 2020, 9, 342 2 of 22 design and has led to the evolution of on-chip interconnection network or network-on-chip (NoC) [3,4]. NoC architecture is a packet-based inter-connected network that separates communication from the computation. As it is different from the shared bus, it facilitates customization in terms of bandwidth, buffers size, and topology. It offers scalability without using long global wires. NoC infrastructure consists of routers and links that are used to deliver packets via layered protocol [5].The continuous improvement in process technology yields higher transistor density [1]. It makes transistors and links more vulnerable to different fault mechanisms [6,7]. A fault in a transistor may lead to erroneous computation. Open/short circuit in links, result in data corruption. Even single fault can paralyze the whole chip. Primarily, faults are classified into permanent and transient categories [8]. Permanent faults are also known as hard faults, apparent in the chip for a lifetime after their occurrence. They permanently affect the functionality of the chip. They are traditionally caused by open/short circuits in links, time-dependent-dielectric-breakdown (TDDB) [9], electro-migration (EM) [10], stress migration, negative-bias-temperature-instability (NBTI) [11], hot carrier injection [12] and thermal cycling [13]. On the other hand, transient faults, also known as soft errors, occur only for on...

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Section: Mdtf Estimation Of Nocguard Routermentioning

confidence: 99%

“…Therefore, input port swapper and bypass bus use reconfiguration to avoid or move additional faults to different data paths. Repair router [25] improves port swapping by using additional buffers. However, it saves only one out of two faulty ports.…”

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confidence: 99%

NoCGuard: A Reliable Network-on-Chip Router Architecture

et al. 2020

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“…On the other hand, the router-level faults use ECC and bypass the bus to tolerate permanent faults in the input buffers and XBAR, respectively. In [ 25 ], the REPAIR router was investigated. It improves the input port swapping algorithm of the Vicis router through expensive re-routing.…”

Section: Related Workmentioning

confidence: 99%

“…We employ pipeline optimization to mask the effect of a faulty arbiter in VA2. In [ 25 ], the authors proposed combining allocation that removes VA2 from the pipeline of the flit. Figure 7 shows the proposed scheme for VA2.…”

Section: Proposed Fault-tolerant Noc Router Architecturementioning

confidence: 99%

Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things

Rashid

Baloch

Shafique

et al. 2020

Sensors

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Network-on-chip (NoC) architectures have become a popular communication platform for heterogeneous computing systems owing to their scalability and high performance. Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. In the proposed scheme, the input port utilizes a bypass path, virtual channel (VC) queuing, and VC closing strategies. Moreover, the routing computation stage utilizes spatial redundancy and double routing strategies, and the VC allocation stage utilizes spatial redundancy. The switch allocation stage utilizes run-time arbiter selection. The crossbar stage utilizes a triple bypass bus. The proposed router is highly fault-tolerant compared with the existing state-of-the-art fault-tolerant routers. The reliability of the proposed router is 7.98 times higher than that of the unprotected baseline router in terms of the mean-time-to-failure metric. The silicon protection factor metric is used to calculate the protection ability of the proposed router. Consequently, it is confirmed that the proposed router has a greater protection ability than the conventional fault-tolerant routers.

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“…A fault-tolerant deflection routing algorithm is proposed to avoid the permanent faults occurring in the router. REPAIR is another router architecture that utilizes some partial redundancies combine with ECC technique to protect the faults in buffers and crossbar switch presented by [32].…”

Section: Related Workmentioning

confidence: 99%

Protector: A Permanent Fault Resilient Router Architecture for Network on Chip

Baloch

Hussain

Baig

2020

Mehran Univ. res. j. eng. technol.

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The decreasing size of the transistor has increased the vulnerability towards faults. Increasing number of cores on a single chip has made the concept of Network on Chip (NoC) a standard communication backbone among cores. This facility comes with vulnerability of faults in the system due to decreasing size of transistors. A permanent fault in the network leads to undesirable consequence such as permanent blocking of flits or failure of the whole router. Preserving the router in the operational state has a significant impact on the reliability of the system. Permanent fault in buffers and pipeline stages of the router has a high impact on performance. The proposed router architecture Protector provides faults protection to both buffers and pipelines stages by exploiting the concepts of borrowing from other resources, using bypass paths and by creating multiple paths to reach output. The proposed router incurred an area overhead of 30% as compared to the baseline design. Reliability analysis using Silicon Protection Factor indicates that the proposed router has better fault tolerance efficiency as compared to state of the art. Latency analysis using PARSEC and SPLASH-2 benchmarks indicates proposed router incurs 13% and 16% latency overhead in the presence of faults.

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REPAIR: A Reliable Partial-Redundancy-Based Router in NoC

Cited by 15 publications

References 8 publications

NoCGuard: A Reliable Network-on-Chip Router Architecture

NoCGuard: A Reliable Network-on-Chip Router Architecture

Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things

Protector: A Permanent Fault Resilient Router Architecture for Network on Chip

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