Repeater and current-sensing hybrid circuits for on-chip interconnects

Abstract

Designing interconnects is becoming an increasingly challenging problem with a few solutions. In this paper hybrid circuit based on the well known delay-optimal repeaters and the recently proposed differential current-sensing is presented. Comparison in terms of delay, power and area is drawn between various versions of the hybrid circuit with delay-optimal repeater insertion and differential current sensing in order to derive at the best possible solution. It is shown that driving 25% of the wire with repeaters and remaining with current-sensing is the best solution from delay standpoint (about 30% faster than delay-optimal repeaters). Not only do hybrid circuits consume less area, they are also a more acceptable solution from placement point of view due to fewer repeaters and a long segment of uninterrupted wire. Static power consumption inherited from differential current-sensing is the biggest drawback of the hybrid circuits.

Mitigating static power in current-sensed interconnects

“…One such current-mode design proposed by [1]is the differential current sense amplifier. It is shown that they perform better in some cases in terms of delay [1] and when combined with 25% repeaters, perform 30% better than conventional delay-optimal repeaters [2]. But their major drawback, as with most differential amplifiers, is static power dissipation.…”