Replication Package for Article: Type-Directed Scheduling of Streaming Accelerators

Durst, David; Feldman, Matthew; Huff, Dillon; Akeley, David; Daly, Ross; Bernstein, Gilbert; Patrignani, Marco; Fatahalian, Kayvon; Hanrahan, Pat

doi:10.1145/3395633

Artifact Digital Object Group 2020

DOI: 10.1145/3395633

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Replication Package for Article: Type-Directed Scheduling of Streaming Accelerators

David Durst¹,

Matthew Feldman²,

Dillon Huff³

et al.

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2023

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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers

Koul

Melchert

Sreedhar

et al. 2023

ACM Trans. Embed. Comput. Syst.

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With the slowing of Moore’s law, computer architects have turned to domain-specific hardware specialization to continue improving the performance and efficiency of computing systems. However, specialization typically entails significant modifications to the software stack to properly leverage the updated hardware. The lack of a structured approach for updating both the compiler and the accelerator in tandem has impeded many attempts to systematize this procedure. We propose a new approach to enable flexible and evolvable domain-specific hardware specialization based on coarse-grained reconfigurable arrays (CGRAs). Our agile methodology employs a combination of new programming languages and formal methods to automatically generate the accelerator hardware and its compiler from a single source of truth. This enables the creation of design-space exploration frameworks that automatically generate accelerator architectures that approach the efficiencies of hand-designed accelerators, with a significantly lower design effort for both hardware and compiler generation. Our current system accelerates dense linear algebra applications, but is modular and can be extended to support other domains. Our methodology has the potential to significantly improve the productivity of hardware-software engineering teams and enable quicker customization and deployment of complex accelerator-rich computing systems.

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AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers

Koul

Melchert

Sreedhar

et al. 2023

ACM Trans. Embed. Comput. Syst.

View full text Add to dashboard Cite

show abstract

Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration

Zacharopoulos

Ejjeh

Jing

et al. 2023

ACM Trans. Embed. Comput. Syst.

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The design of heterogeneous systems that include domain specific accelerators is a challenging and time-consuming process. While taking into account area constraints, designers must decide which parts of an application to accelerate in hardware and which to leave in software. Moreover, applications in domains such as Extended Reality (XR) offer opportunities for various forms of parallel execution, including loop level, task level and pipeline parallelism. To assist the design process and expose every possible level of parallelism, we present Trireme , a fully automated tool-chain that explores multiple levels of parallelism and produces domain specific accelerator designs and configurations that maximize performance, given an area budget. FPGA SoCs were used as target platforms and Catapult HLS [7] was used to synthesize RTL using a commercial 12nm FinFET technology. Experiments on demanding benchmarks from the XR domain revealed a speedup of up to 20 ×, as well as a speedup of up to 37 × for smaller applications, compared to software-only implementations.

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Replication Package for Article: Type-Directed Scheduling of Streaming Accelerators

Cited by 2 publications

References 0 publications

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers

Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration

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