Representation of type I heterostructure junctionless tunnel field effect transistor for high-performance logic application

Abadi, Rouzbeh Molaei Imen; Ziabari, Seyed Ali Sedigh

doi:10.1007/s00339-016-0151-3

Cited by 23 publications

(2 citation statements)

References 27 publications

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“…In order to overcome these drawbacks, various techniques have been reported in earlier research works i.e. bandgap engineering [23][24][25], double-gate architecture [26,27], gate work function engineering [28][29][30][31][32], hetero-dielectric TFET [33,34], strain channel engineering [35,36], different geometries such as L-shaped and U-shaped channel TFET [37][38][39][40][41][42][43][44][45] and so on. In this paper, we have proposed a novel TFET design with a linear-doped channel double-step structure for the first time.…”

Section: Introductionmentioning

confidence: 99%

Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: a 2D numerical simulation study

Meshkin¹,

Ziabari²,

Jordehi³

2020

Semicond. Sci. Technol.

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In this paper, a novel double-step (DS) structure tunnel field-effect transistor with a linear doping profile channel (DSS-LDC-TFET) is presented. The use of a step-shaped structure near the source/channel interface leads to the large tunneling junction area because the band-to-band tunneling of the carriers occurs perpendicularly along the conducting path in the channel. The step-shape of the channel/drain interface reduces the electric field distribution near the drain junction which helps to suppress the ambipolar behavior. Further, the DS structure of the body suppresses the ambipolar conduction due to increasing the effective length of channel area along the device. Therefore, the height of the steps in the proposed structure plays an important role in the device characteristics. The doping profile in the channel region is considered to be linear. The maximum value of the doping concentration is at the source side and linearly decreases to its minimum value along the x-axis. Numerical simulation results show that using the linear doping distribution at the channel improves device behavior through reducing the tunneling barrier width at the source/channel interface. The optimum length for the linear-doped part of the channel is selected to maximize the on-state current without degrading much the off-state current. Finally, the comparative study between DSS-LDC-TFET with the conventional silicon-on-insulator tunnel field-effect transistor is presented.

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Section: Introductionmentioning

confidence: 99%

Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: a 2D numerical simulation study

Meshkin¹,

Ziabari²,

Jordehi³

2020

Semicond. Sci. Technol.

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“…In order to improve the characteristics of JLFET, different junctionless structures are available in the literature such as, silicon-on-insulator (SOI) JLFET [24,25], bulk-planner JLFET [26,27], CNT-based JLFET [28], multi-gate transistors [29,30] and gate-all-around transistors [31,32]. Recently, because of a low power demand over the last few decades, alternative transistor namely as silicon-based junctionless tunnel field effect transistor has been represented [33][34][35][36]. The junctionless TFET has been proposed as a solution for the various problems encountered in conventional CMOS technology such as scalability, low SS, and ON/OFF current ratio.…”

Section: Introductionmentioning

confidence: 99%

A Comparative Numerical Study of Junctionless and p-i-n Tunneling Carbon Nanotube Field Effect Transistor

Abadi

Ziabari

2017

JNanoR

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In this paper, a gate-all-around junctionless tunnel field effect transistor (JL-TFET) based on carbon nanotube (CNT) material is introduced and simulated. The JL-TFET is a CNT-channel heavily n-type-doped junctionless field effect transistor (JLFET) which utilizes two insulated gates (Control-Gate, P-Gate) with two different metal workfunctions in order to treat like tunnel field effect transistor (TFET). In this design, the privileges of JLTFET and TFET are mixed together. The numerical comparative study on the performance characteristics of JL-TFET and conventional p-i-n TFET demonstrated that the proposed JL-TFET has a higher ON-state current driveability (ION), a larger ON/OFF-current ratio (ION/IOFF), a lower drain induced barrier lowering (DIBL), a shorter delay time (τ), and also a superior cut-off frequency (ƒT). Moreover, in order to further performance improvement of proposed JLTFET, three novel device structures namely as junctionless linear descending gate workfunction TFET (JL-LDWTFET), junctionless linear ascending gate workfunction TFET (JL-LAWTFET) and junctionless triple metal gate TFET (JL-TMGTFET) are proposed by gate workfunction engineering approach. According to simulation results, the JL-TMGTFET with the gate composed of three segments of different work functions shows excellent characteristics with high ION/IOFF ratio, a superior ambipolar characteristic, a shorter delay time and a better cut-off frequency compared to conventional p-i-n TFET and other proposed junctionless-based features. All the simulations are done with the full quantum mechanical simulator for a channel length of 60-nm using nonequilibrium Green’s function (NEGF) method.

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Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

Abadi

Ziabari

2016

Appl. Phys. A

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Representation of type I heterostructure junctionless tunnel field effect transistor for high-performance logic application

Cited by 23 publications

References 27 publications

Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: a 2D numerical simulation study

Representation of an engineered double-step structure SOI-TFET with linear doped channel for electrical performance improvement: a 2D numerical simulation study

A Comparative Numerical Study of Junctionless and p-i-n Tunneling Carbon Nanotube Field Effect Transistor

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

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