Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation

DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

“…Duwe et al focus on the tolerance of faults in a CPU cache-like structure [15]. With the aim to improve the ECC correction capability, this approach reorders the bits within a cache line in such a way that ECC is able to generate a correction code.…”

Exploiting intrinsic hardware guardbands and software heterogeneity to improve the energy efficiency of computing systems

“…Several proposed techniques present design approaches at the circuit or microarchitectural level that trade reliability for lower voltage, by attempting to reduce the voltage down to the point that produces maximum allowable errors without causing catastrophic failures [79]. Several approaches propose methods that ensure the correct operation of caches under undervolted conditions at the microarchitectural level [80,81,82]. Architectural techniques are presented to eliminate data corruption, and by extension enable cache operation at scaled voltage settings.…”

Anatomy of microarchitecture-level reliability assessment for modern processors

“…Methods for Improved SRAM Reliability: Authors in [121] [122] and [133] propose several microarchitectural approaches to ensure the correct operation of caches in ultralow voltage conditions. Abella et al [134] proposed a disabling-and-remapping approach for cache arrays to deliver predictable performance at low voltages.…”