Research and measurement of chip current imbalance in IGBT module with multiple chips in parallel

Abstract

the current sharing of the chips in parallel is one of the key points of the layout design of IGBT module. The current imbalance of the chips leads to imbalance losses and temperature, and increases the failure of the chip with highest temperature, so attention should be paid during the IGBT module design. In this paper, the asymmetric stray parameters of the circuit in parallel and the coupling between the gate circuit and the power circuit are analyzed by the equivalent circuit method, but the simulation results and the experimental results show that the stray inductances and resistances, extracted at the fixed frequency, can't reflect the electrical behaviors of the power and gate circuit. A method to extract the stray parameters is proposed in this paper, which can be used to reflect the current imbalance of the switching and conducting behaviors.(a) The geometry of IGBT module A

The Research on over current switch-off simulation of IGBT level in parallel connection

“…Besides, The current of the IGBT1 is twice more than the rated current, when the stray inductance is significantly increased. It is likely to cause IGBT1 over current failure, thereby destroying the whole module [5]. …”

Recent progress in deep-depletion diamond metal–oxide–semiconductor field-effect transistors

“…However, this should be mitigated when paralleling FET cells on the same diamond die, due to their large thermal conductivity and the high thermal coupling between elementary transistors. Nonetheless, a careful design must be done for the forthcoming diamond power modules, which will be similar to Si, GaN, SiC modules [84][85][86][87] but with the physical parameters of diamond devices, such as the NTC behavior. received funding from the Clean Sky 2 Joint Undertaking (JU) under grant agreement No 101007868.…”