Research on testing of a microsystem based on SiP

Abstract

System in Package (SiP) technology satisfies the further increasing demand by integration of different functions into one unit to reduce size and improve functionality. But the disadvantages of SiP are also increased risks in reliability, manufacturability, and difficulty with test access. A complete final test is necessary before its application. This paper presents a functional test scheme for a mircosystem based on 3D-SiP. Test system consists of a test board designed specifically and Cygwin environment of PC in debug support unit (DSU) and JTAG TAP techniques. It allows the complete final system-testing carry out in a fast, flexible, and nondestructive way. And it can improve the testability and reliability of microsystem.

Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard

“…Our SiP system is consists of four layers [5], which are CPU layer, SRAM layer, Flash layer and bus interface layer which is shown in Fig.3. CPU layer integrates a processor and several specific IPs which connected by AMBA bus.…”