Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects

Venuturupalli, Pankaj; Govindaswamy, Prema Kumar; Pasupureddi, Vijaya Sankara Rao

doi:10.1016/j.mejo.2020.104899

Microelectronics Journal

2020

DOI: 10.1016/j.mejo.2020.104899

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Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects

Pankaj Venuturupalli

Prema Kumar Govindaswamy

Vijaya Sankara Rao Pasupureddi

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2023

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“…The resistance, inductance and capacitance (RLC) equivalent circuit of interconnect.T A B L E 1 The 3-dB cutoff frequency and delay for different lengths of the interconnect 21. PROPOSED ADAPTIVE LINK TRAINING BASED HYBRID CIRCUIT TOPOLOGYThis section describes the proposed half-rate DCSLH circuit topology with an adaptation link training scheme.…”

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An adaptive link training based hybrid circuit topology for full‐duplex on‐chip interconnects

Govindaswamy

Kammari

Pasupureddi

2023

Circuit Theory & Apps

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SummaryThis work proposes a link training based half‐rate dynamic current‐steering echo‐cancellation hybrid circuit topology for full‐duplex signaling that performs echo cancellation by deploying a bit error detection unit and backchannel adaptation. In addition, this work proposes a power‐efficient half‐rate dynamic current‐steering logic hybrid circuit for full‐duplex signaling over on‐chip interconnects for simultaneous transmission and reception. The half‐rate dynamic current‐steering hybrid circuit topology has low static power consumption compared with traditional current‐mode circuit topology implementations, thanks to the discrete nature of the current‐steering hybrid topology. The proposed scheme is implemented in 1.2 V, 65‐nm complementary metal‐oxide semiconductor (CMOS). The performance results show that the link training scheme sets the control bits for both the transmitter driver and hybrid circuit topology when the backchannel adaptation loop gets locked for 1‐ and 3‐mm interconnects for process, voltage, and temperature (PVT) variations. The proposed hybrid circuit topology is able to receive the required far‐end transmitted data with the link training scheme and has the differential recovered received signal voltage swing of 1.2 V for both 1‐ and 3‐mm interconnect at the 10‐Gb/s data rate. The total power consumption of the hybrid is 3 and 3.5 mW for 1‐ and 3‐mm interconnect with an energy efficiency of 0.6 and 0.7 pJ/bit, respectively, at 10‐Gb/s full‐duplex operation.

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confidence: 99%

An adaptive link training based hybrid circuit topology for full‐duplex on‐chip interconnects

Govindaswamy

Kammari

Pasupureddi

2023

Circuit Theory & Apps

Self Cite

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Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects

Cited by 1 publication

References 6 publications

An adaptive link training based hybrid circuit topology for full‐duplex on‐chip interconnects

An adaptive link training based hybrid circuit topology for full‐duplex on‐chip interconnects

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