2016
DOI: 10.1007/s10470-016-0859-1
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Resilient design of current steering DACs using a transistor level approach

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Cited by 11 publications
(8 citation statements)
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“…Table lists some obtained structures with minimum power consumption. As it is declared that opamp scaling is not as effective as capacitor value in power consumption, this factor is not considered here .…”
Section: Experimental Implementation and Resultsmentioning
confidence: 99%
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“…Table lists some obtained structures with minimum power consumption. As it is declared that opamp scaling is not as effective as capacitor value in power consumption, this factor is not considered here .…”
Section: Experimental Implementation and Resultsmentioning
confidence: 99%
“… eKTtrue/C,i2=KTCfi+nCsi where C fi and C si are the i th stage feedback and sampling capacitors in order. The total input referred noise power for a k ‐stage pipeline ADC can be obtained as follows . eKTtrue/C,italictotal2=eKTtrue/C,12+eKT/C,22G12+eKT/C,32G12.G22+prefix+eKT/C,k2i=1k1Gi2 …”
Section: Experimental Implementation and Resultsmentioning
confidence: 99%
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“…It was provided with a 3.3V power supply and observed 0.6 LSB OF INL. [15] proposed a design of steering DAC. It was provided with transistor level synthesis.…”
Section: Introductionmentioning
confidence: 99%